static void mtt_reset(SkelDrvrModuleContext *mcon)
{
InsLibIntrDesc *isr = mcon->Modld->Isr;
struct udata *udata = mcon->UserData;
unsigned long flags;
cdcm_spin_lock_irqsave(&udata->iolock, flags);
/* quiesce the module */
__mtt_quiesce(mcon);
/* reset the module */
__mtt_cmd(mcon, MttDrvrCommandRESET, 1);
__mtt_cmd(mcon, MttDrvrCommandENABLE, 1);
udata->EnabledOutput = 1;
cdcm_spin_unlock_irqrestore(&udata->iolock, flags);
usec_sleep(100);
/*
* re-configure the interrupt level
* Note that the vector and level share the register
*/
if (isr) {
mtt_writew(mcon, MTT_INTR, isr->Vector |
mtt_shift_intr_level(isr->Level));
}
}
/* Ensure the command is executed atomically by acquiring the module's iolock */
static inline void
mtt_cmd(SkelDrvrModuleContext *mcon, uint32_t cmd, uint32_t val)
{
struct udata *udata = mcon->UserData;
unsigned long flags;
cdcm_spin_lock_irqsave(&udata->iolock, flags);
__mtt_cmd(mcon, cmd, val);
cdcm_spin_unlock_irqrestore(&udata->iolock, flags);
}
static void mtt_gs_utc(SkelDrvrModuleContext *mcon, MttDrvrTime *utc, int set)
{
struct udata *udata = mcon->UserData;
unsigned long flags;
cdcm_spin_lock_irqsave(&udata->iolock, flags);
if (set) {
__mtt_cmd(mcon, MttDrvrCommandSET_UTC, utc->Second);
} else {
/* reading the ms register causes the seconds to be latched */
utc->MilliSecond = mtt_readw(mcon, MTT_MSEC);
cdcm_wmb();
utc->Second = mtt_readw(mcon, MTT_SEC);
}
cdcm_spin_unlock_irqrestore(&udata->iolock, flags);
}
