int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3DIR |= BIT0; // P3.0 output direction
P3SEL |= BIT0; // Select CBOUT function on P3.0/CBOUT
// Setup ComparatorB
CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0
CBCTL1 |= CBPWRMD_1; // normal power mode
CBCTL2 |= CBRSEL; // VREF is applied to -terminal
CBCTL2 |= CBRS_3+CBREFL_2; // R-ladder off; bandgap ref voltage (1.2V)
// supplied ref amplifier to get Vcref=2.0V (CBREFL_2)
CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0
CBCTL1 |= CBON; // Turn On ComparatorB
__delay_cycles(75); // delay for the reference to settle
__bis_SR_register(LPM4_bits); // Enter LPM4
__no_operation(); // For debug
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
// unsigned multiply
MPY32L = 0x1234; // Load lower 16 bits of operand 1
MPY32H = 0x1234; // Load upper 16 bits of operand 1
OP2L = 0x5678; // Load lower 16 bits of operand 2
OP2H = 0x5678; // Load upper 16 bits of operand 2
// unsigned MAC
MAC32L = 0x1234; // Load lower 16 bits of operand 1
MAC32H = 0x1234; // Load upper 16 bits of operand 1
OP2L = 0x5678; // Load lower 16 bits of operand 2
OP2H = 0x5678; // Load upper 16 bits of operand 2
__bis_SR_register(LPM4_bits); // Enter LPM4
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1DIR |= BIT6; // P1.6/CBOUT output direction
P1SEL |= BIT6; // Select CBOUT function on P1.6/CBOUT
// Setup ComparatorB
CBCTL0 |= CBIPEN+CBIPSEL_0; // Enable V+, input channel CB0
CBCTL1 |= CBMRVS; // CMRVL selects the refV - VREF0
CBCTL1 |= CBPWRMD_2; // Ultra-Low Power mode
CBCTL2 |= CBRSEL; // VREF is applied to -terminal
CBCTL2 |= CBRS_1+CBREF04; // VCC applied to R-ladder; VREF0 is Vcc*1/2
CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0
CBCTL1 |= CBON; // Turn On ComparatorB
__delay_cycles(75); // delay for the reference to settle
__bis_SR_register(LPM4_bits); // Enter LPM4
__no_operation(); // For debug
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
ADC10CTL1 = INCH_10 + ADC10DIV_3; // ADC Channel -> 10 (Temp Sensor), CLK/4
ADC10CTL0 = SREF_1 + ADC10SHT_3 + REFON + ADC10ON + ADC10IE;
// Ref -> 1.5V, 64 CLK S&H, Interrupt Enabled
__delay_cycles(100); // Wait for reference to settle
while(1)
{
ADC10CTL0 |= ENC + ADC10SC; // Sampling and conversion start
__bis_SR_register(CPUOFF + GIE); // LPM0 with interrupts enabled
adcValue = ADC10MEM; // Fetch ADC conversion result
// C = ( (adcValue/1024)*1500mV)-986mV)*1/3.55mV
tempC = ((adcValue - 673) * 423) / 1024;
__no_operation(); // Required for breakpoint
}
}
/**
* @fn unsigned char PortEventHandler(const void * params)
*
* @brief This function is an extension of GPIO Port ISR.
*
* @param params a constant void pointer
*
* @return an unsigned character
*/
unsigned char PortEventHandler(const void * params)
{
// Get event parameters.
EventParameters * p = (EventParameters *) params;
if (p->event & __BSP_PUSHBUTTON1_EVENT)
{
PushButtonEventHandler(__BSP_PUSHBUTTON1, __BSP_CONFIG_PUSHBUTTON_MINIMUM_CLICK_TIME);
}
if (p->event & __BSP_RADIO1_GDO0_EVENT)
{
volatile unsigned char tempVar = 0;
if(__BSP_RADIO1_GDO0_EVENT & __BSP_RADIO1_GDO0_EDGE_SELECT) // End of Packet
{
if(pCurrentFrameworkRadio(&appRadio[RadioLocal.currentRadio])->radioState == RADIO_TRANSMIT){
RadioLocal.FrameState = FRAME_SENT; // Update frame state
//GDO0 asserted slightly before RF transmission ends, so add a little delay
for(tempVar=0;tempVar<200;tempVar++){
__no_operation();
}
}
else if(pCurrentFrameworkRadio(&appRadio[RadioLocal.currentRadio])->radioState == RADIO_RECEIVE){
RadioLocal.FrameState = FRAME_RECEIVED; // Update frame state
TimerCCRDisableInterrupt(__BSP_TIMER1, __BSP_TIMER1_CCR1);
}
pCurrentFrameworkRadio(&appRadio[RadioLocal.currentRadio])->radioState = RADIO_CALIBRATED;
}
else // SyncWord sent/received
{
RadioSetInterruptEdge(pCurrentFrameworkRadio(&appRadio[RadioLocal.currentRadio]), __BSP_RADIO1_INTERRUPT1, 1);
RadioLocal.FrameState = WAITING_FOR_EOP; // Update frame state
StartTimeoutTimer(EOP_TIMEOUT); // Load timer with timeout value. The radio should be placed in a low-power state if frame timeout occurs.
}
}
return EVENT_WAKE_UP;
}
void main(void)
{
WDTCTL = WDT_ADLY_1000; // WDT 1000ms, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCA0RXD; // Map UCA0RXD output to P2.6
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to UART function
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 9; // 1MHz 115200 (see User's Guide)
UCA0BR1 = 0; // 1MHz 115200
UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
DMACTL0 = DMA1TSEL_16+DMA0TSEL_17; // DMA0 - UCA0TXIFG
// DMA1 - UCA0RXIFG
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &TxString);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA0TXBUF);
// Destination single address
DMA0SZ = 1; // Block size
DMA0CTL = DMASRCINCR_0+DMASBDB+DMALEVEL; // src does not change
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &UCA0RXBUF);
// Source block address
__data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &RxString);
// Destination single address
DMA1SZ = 1; // Block size
DMA1CTL = DMADSTINCR_0+DMASBDB+DMALEVEL+DMADT_4+DMAEN; // dst does not change
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
// Configure ADC10;
ADC10CTL0 = ADC10SHT_3 + ADC10MSC + ADC10ON;// 32ADCclks, ADC on
ADC10CTL1 = ADC10SHP + ADC10CONSEQ_2 + ADC10SSEL_3 + ADC10DIV_1; // SMCLK/2
// Sampling timer, rpt single ch
ADC10CTL2 = ADC10RES; // 10-bit resolution
ADC10MCTL0 = ADC10INCH_11 + ADC10SREF_1; // Vref+, A10
// Configure internal reference
while(REFCTL0 & REFGENBUSY); // If ref generator busy, WAIT
REFCTL0 |= REFVSEL_0+REFON; // Select internal ref = 1.5V
// Internal Reference ON
__delay_cycles(75); // Delay (~75us) for Ref to settle
// Configure DMA (ADC10IFG trigger)
DMACTL0 = DMA0TSEL_24; // ADC10IFG trigger
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &ADC10MEM0);
// Source single address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) 0x1800);
// Destination array address
DMA0SZ = 0x20; // 32 conversions
DMA0CTL = DMADT_4 + DMADSTINCR_3 + DMAEN + DMAIE; // Rpt, inc dest, word access,
// enable int after 32 conversions
while(1)
{
FCTL3 = FWKEY; // Lock = 0
FCTL1 = FWKEY + ERASE; // Erase bit = 1
*(unsigned int *)0x1800 = 0; // Dummy write to erase Flash seg
while (ADC10CTL1 & BUSY); // Wait if ADC10 core is active
FCTL1 = FWKEY + WRT; // Write bit = 1
ADC10CTL0 |= ADC10ENC + ADC10SC; // Start sampling
__bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit
FCTL3 = FWKEY + LOCK; // Lock = 1
__no_operation(); // << SET BREAKPOINT HERE
__delay_cycles(5000); // Delay between conversions
}
}
__interrupt void RTC_isr(void)
{
switch(__even_in_range(RTCIV,14))
{
case 0: break; // Vector 0: No interrupt
case 2: // Vector 2: RTCRDYIFG
__no_operation();
break;
case 4: break; // Vector 4: RTCEVIFG
case 6: break; // Vector 6: RTCAIFG
case 8: break; // Vector 8: RT0PSIFG
case 10: break; // Vector 10: RT1PSIFG
case 12: break; // Vector 12: RTCOFIFG
case 14: break; // Vector 14: Reserved
default: break;
}
#ifdef USE_LOW_POWER_MODE
LPM_disable(); // Wake-up MCU
#endif
}
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
UCSCTL4 = SELA_1; // Ensure VLO is ACLK source
// Port Configuration
P1OUT = 0x00;P2OUT = 0x00;P3OUT = 0x00;P4OUT = 0x00;P5OUT = 0x00;P6OUT = 0x00;
P7OUT = 0x00;P8OUT = 0x00;P9OUT = 0x00;PJOUT = 0x00;
P1DIR = 0xFF;P2DIR = 0xFF;P3DIR = 0xFF;P4DIR = 0xFF;P5DIR = 0xFF;P6DIR = 0xFF;
P7DIR = 0xFF;P8DIR = 0xFF;P9DIR = 0xFF;PJDIR = 0xFF;
// Disable VUSB LDO and SLDO
USBKEYPID = 0x9628; // set USB KEYandPID to 0x9628
// enable access to USB config reg
USBPWRCTL &= ~(SLDOEN+VUSBEN); // Disable the VUSB LDO and the SLDO
USBKEYPID = 0x9600; // disable access to USB config reg
__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}
int main(void)
{
WDTCTL = WDTPW | WDTHOLD;
// Configure GPIO
P1SEL1 |= BIT6 | BIT7; // I2C pins
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
// Configure USCI_B0 for I2C mode
UCB0CTLW0 = UCSWRST; // Software reset enabled
UCB0CTLW0 |= UCMODE_3 | UCSYNC; // I2C mode, sync mode
UCB0I2COA0 = 0x48 | UCOAEN; // own address is 0x48 + enable
UCB0CTLW0 &= ~UCSWRST; // clear reset register
UCB0IE |= UCTXIE0 | UCSTPIE; // transmit,stop interrupt enable
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
__no_operation();
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= 0x06; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMODE_3 + UCSYNC; // I2C Slave, synchronous mode
UCB0I2COA = 0x48; // Own Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCSTPIE + UCSTTIE + UCRXIE; // Enable STT, STP & RX interrupt
while (1)
{
PRxData = (unsigned char *)RxBuffer; // Start of RX buffer
RXByteCtr = 0; // Clear RX byte count
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0, enable interrupts
// Remain in LPM0 until master
// finishes TX
__no_operation(); // Set breakpoint >>here<< and read
} // read out the RxData buffer
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL |= BIT1+BIT2; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMODE_3 + UCSYNC; // I2C Slave, synchronous mode
UCB0I2COA = 0x48; // Own Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0I2CIE |= UCSTPIE + UCSTTIE; // Enable STT and STP interrupt
IE2 |= UCB0TXIE; // Enable TX interrupt
while (1)
{
PTxData = (unsigned char *)TxData; // Start of TX buffer
TXByteCtr = 0; // Clear TX byte count
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
// Remain in LPM0 until master
// finishes RX
__no_operation(); // Set breakpoint >>here<< and
} // read out the TXByteCtr counter
}
// Main Function
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
// establish baseline
TI_CAPT_Init_Baseline(&slider);
TI_CAPT_Update_Baseline(&slider,5);
// Main loop starts here
while (1)
{
position = TI_CAPT_Slider(&slider);
//TI_CAPT_Custom(&slider,dCnt);
if(position != ILLEGAL_SLIDER_WHEEL_POSITION)
{
__no_operation();
}
__delay_cycles(100);
}
} // End Main
void main(void)
{
WDTCTL = WDT_ADLY_1000; // WDT 1000ms, ACLK, interval timer
SFRIE1 |= WDTIE; // Enable WDT interrupt
P1OUT &= ~0x01; // Clear P1.0
P1DIR |= 0x01; // P1.0 = Output
P3SEL |= 0x31; // P3.0,4,5 = USCI_A0 SPI Option
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 = UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTL1 = UCSSEL_2; // SMCLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0x00; //
UCA0MCTL = 0x00; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
DMACTL0 = DMA1TSEL_16+DMA0TSEL_17; // DMA0 - UCA0TXIFG
// DMA1 - UCA0RXIFG
// Setup DMA0
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &TxString);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &UCA0TXBUF);
// Destination single address
DMA0SZ = 1; // Block size
DMA0CTL = DMASRCINCR_3+DMASBDB+DMALEVEL; // inc src
// Setup DMA1
__data16_write_addr((unsigned short) &DMA1SA,(unsigned long) &UCA0RXBUF);
// Source block address
__data16_write_addr((unsigned short) &DMA1DA,(unsigned long) &RxString);
// Destination single address
DMA1SZ = 1; // Block size
DMA1CTL = DMADSTINCR_3+DMASBDB+DMALEVEL; // inc dst
TxString = RxString = 0; // Clear TxString
// Clear RxString
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3 w/ interrupts
__no_operation(); // Required only for debugger
}
int main (void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1DIR |= BIT0; // P1.0 Output
P1OUT &= ~BIT0; // Clear LED to start
// Init CRC
CRCINIRES = CRC_Init; // Init CRC with 0xFFFF
for(i=0;i<16;i++)
{
// Input random values into CRC Hardware
CRCDIRB = CRC_Input[i]; // Input data in CRC
__no_operation();
}
CRC_Results = CRCINIRES; // Save results (per CRC-CCITT standard)
for(i=0;i<16;i++)
{
// Input values into Software algorithm (requires 8-bit inputs)
unsigned int LowByte = (CRC_Input[i] & 0x00FF); // Clear upper 8 bits to get lower byte
unsigned int UpByte = (CRC_Input[i] >> 8); // Shift right 8 bits to get upper byte
// First input lower byte
if(i==0)
CRC_New = CCITT_Update(CRC_Init,LowByte);
else
CRC_New = CCITT_Update(CRC_New,LowByte);
// Then input upper byte
CRC_New = CCITT_Update(CRC_New,UpByte);
}
SW_Results = CRC_New;
// Compare data output results
if(CRC_Results==SW_Results) // if data is equal
P1OUT |= BIT0; // set the LED
else
P1OUT &= ~BIT0; // if not, clear LED
while(1); // infinite loop
}
void main(void)
{
unsigned char i;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P3SEL = BIT3+BIT4; // P3.4,5 = USCI_A0 TXD/RXD
//.......................
// P5SEL |= BIT4+BIT5; // Select XT1
//
// UCSCTL6 &= ~(XT1OFF); // XT1 On
// UCSCTL6 |= XCAP_3; // Internal load cap
// UCSCTL3 = 0; // FLL Reference Clock = XT1
//
// // Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
// do
// {
// UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// // Clear XT2,XT1,DCO fault flags
// SFRIFG1 &= ~OFIFG; // Clear fault flags
// }while (SFRIFG1&OFIFG); // Test oscillator fault flag
//
// UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive strength
//
// UCSCTL4 |= SELA_0 + SELS_4 + SELM_4; // ACLK = LFTX1
// // SMCLK = default DCO
// // MCLK = default DCO
//
//................
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_1; // CLK = ACLK
UCA0BR0 = 0x03; // 32kHz/9600=3.41 (see User's Guide)
UCA0BR1 = 0x00; //
UCA0MCTL = UCBRS_3+UCBRF_0; // Modulation UCBRSx=3, UCBRFx=0
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, interrupts enabled
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
// Enable XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKIO);
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive
// strength
UCSCTL4 &= ~(SELA0 + SELA1 + SELA2); // Ensure XT1 is ACLK source
// Port Configuration
P1OUT = 0x00;P2OUT = 0x00;P3OUT = 0x00;P4OUT = 0x00;P5OUT = 0x00;P6OUT = 0x00;
P7OUT = 0x00;P8OUT = 0x00;P9OUT = 0x00;PJOUT = 0x00;
P1DIR = 0xFF;P2DIR = 0xFF;P3DIR = 0xFF;P4DIR = 0xFF;P5DIR = 0xFF;P6DIR = 0xFF;
P7DIR = 0xFF;P8DIR = 0xFF;P9DIR = 0xFF;PJDIR = 0xFF;
// Disable VUSB LDO and SLDO
USBKEYPID = 0x9628; // set USB KEYandPID to 0x9628
// enable access to USB config reg
USBPWRCTL &= ~(SLDOEN+VUSBEN); // Disable the VUSB LDO and the SLDO
USBKEYPID = 0x9600; // disable access to USB config reg
// Disable SVS
PMMCTL0_H = PMMPW_H; // PMM Password
SVSMHCTL &= ~(SVMHE+SVSHE); // Disable High side SVS
SVSMLCTL &= ~(SVMLE+SVSLE); // Disable Low side SVS
__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}
void main (void)
{
//Stop WDT
WDT_hold(__MSP430_BASEADDRESS_WDT_A__);
//Select CBOUT function on P1.6/CBOUT and set P1.6 output direction
GPIO_setAsPeripheralModuleFunctionOutputPin(__MSP430_BASEADDRESS_PORT1_R__,
GPIO_PORT_P1,
GPIO_PIN6
);
//Initialize the Comparator B module
/*
* Base Address of Comparator B,
* Pin CB0 to Positive(+) Terminal,
* Reference Voltage to Negative(-) Terminal,
* Normal Power Mode,
* Output Filter On with minimal delay,
* Non-Inverted Output Polarity
*/
COMPB_init(__MSP430_BASEADDRESS_COMPB__,
COMPB_INPUT0,
COMPB_INPUT1,
COMPB_POWERMODE_NORMALMODE,
COMPB_FILTEROUTPUT_DLYLVL1,
COMPB_NORMALOUTPUTPOLARITY
);
//Allow power to Comparator module
COMPB_enable(__MSP430_BASEADDRESS_COMPB__);
//delay for the reference to settle
__delay_cycles(75);
//Enter LPM4
__bis_SR_register(LPM4_bits);
//For debug
__no_operation();
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
BCSCTL1 = CALBC1_1MHZ; // Set DCO to 1MHz
DCOCTL = CALDCO_1MHZ;
FCTL2 = FWKEY + FSSEL0 + FN1; // MCLK/3 for Flash Timing Generator
P1DIR |= 0x01; // P1.0 output
TACCTL0 = CCIE; // TACCR0 interrupt enabled
TACCR0 = 50000;
TACTL = TASSEL_2 + MC_1; // SMCLK, upmode
value = 0; // Initialize value
__enable_interrupt(); // Enable interrupts
while(1) // Repeat forever
{
write_SegD(value++); // Write segment D, increment value
copy_D2A(); // Copy segment D to A
copy_D2B(); // Copy segment D to B
copy_D2C(); // Copy segment D to C
__no_operation(); // Set breakpoint here
}
}
void main(void)
{
// Stop watchdog timer
WDTCTL = WDTPW + WDTHOLD;
// Temperature Sensor ADC10CLK/4
ADC10CTL1 = INCH_10 + ADC10DIV_3;
// Ref voltage/sample & hold time/
// reference generator ON/ADC10 ON
ADC10CTL0 = SREF_1 + ADC10SHT_3 + REFON + ADC10ON;
while(1) {
// Sampling and conversion start
ADC10CTL0 |= ENC + ADC10SC;
// Waint for ADC to complete
while(ADC10CTL1 & ADC10BUSY);
// Read ADC sample
sample = ADC10MEM;
DegreeF = ((sample - 630) * 761) / 1024;
// SET BREAKPOINT HERE
__no_operation();
}
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCB0SDA; // Map UCB0SDA output to P2.6
P2MAP7 = PM_UCB0SCL; // Map UCB0SCL output to P2.7
PMAPPWD = 0; // Lock port mapping registers
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to I2C function
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMODE_3 + UCSYNC; // I2C Slave, synchronous mode
UCB0I2COA = 0x48; // Own Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCTXIE + UCSTTIE + UCSTPIE; // Enable TX interrupt
// Enable Start condition interrupt
TXData = 0; // Used to hold TX data
__bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
// Set up XT1
P5SEL |= BIT4+BIT5; // Select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
P1DIR |= BIT0; // P1.0 output
RTCCTL01 = RTCTEV_3;
RTCPS0CTL = RT0PSDIV_7; // Set RTPS0 to /256
RTCPS1CTL = RT1IP_6 + RT1PSIE + RT1SSEL_3;// Set RT1IP to /4, enable
// RT1PS interrupt and select
// RTOPS output as clock
SFRIE1 = OFIE; // Enable osc fault interrupt
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Hold WDT
P1OUT &= ~BIT0; // P1.0 clear
P1DIR |= BIT0; // P1.0 output
P5SEL |= BIT7; // P5.7/TB1 option select
P5DIR |= BIT7; // Output direction
P6SEL |= BIT0; // Enable A/D channel A0
//Setup Timer B0
TBCCR0 = 0xFFFE;
TBCCR1 = 0x8000;
TBCCTL1 = OUTMOD_3; // CCR1 set/reset mode
TBCTL = TBSSEL_2+MC_1+TBCLR; // SMCLK, Up-Mode
// Setup ADC12
ADC12CTL0 = ADC12SHT0_15+ADC12MSC+ADC12ON;// Sampling time, MSC, ADC12 on
ADC12CTL1 = ADC12SHS_3+ADC12CONSEQ_2; // Use sampling timer; ADC12MEM0
// Sample-and-hold source = CCI0B =
// TBCCR1 output
// Repeated-single-channel
ADC12MCTL0 = ADC12SREF_0+ADC12INCH_0; // V+=AVcc V-=AVss, A0 channel
ADC12CTL0 |= ADC12ENC;
// Setup DMA0
DMACTL0 = DMA0TSEL_24; // ADC12IFGx triggered
DMACTL4 = DMARMWDIS; // Read-modify-write disable
DMA0CTL &= ~DMAIFG;
DMA0CTL = DMADT_4+DMAEN+DMADSTINCR_3+DMAIE; // Rpt single tranfer, inc dst, Int
DMA0SZ = 1; // DMA0 size = 1
__data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &ADC12MEM0);
// Source block address
__data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &DMA_DST);
// Destination single address
__bis_SR_register(LPM0_bits + GIE); // LPM0 w/ interrupts
__no_operation(); // used for debugging
}
/**********************************************************************//**
* @brief Calibrate thermistor or accelerometer
*
* @param none
*
* @return none
*************************************************************************/
unsigned int CalibrateADC(void)
{
unsigned char CalibCounter =0;
unsigned int Value = 0;
// Disable interrupts & user input during calibration
DisableSwitches();
while(CalibCounter <50)
{
P3OUT ^= BIT4;
CalibCounter++;
while (ADC10CTL1 & BUSY);
ADC10CTL0 |= ADC10ENC | ADC10SC ; // Start conversion
__bis_SR_register(CPUOFF + GIE); // LPM0, ADC10_ISR will force exit
__no_operation();
Value += ADCResult;
}
Value = Value/50;
// Reenable switches after calibration
EnableSwitches();
return Value;
}
void UART_ISR(void)
{
switch(__even_in_range(UCA1IV,0x08))
{
case 0:break; /* Vector 0 - no interrupt */
case 2: /* Vector 2 - RXIFG */
#ifdef _USE_CLI_
*g_ucUARTBuffer = UCA1RXBUF;
if (*g_ucUARTBuffer == ASCII_ENTER)
{
cli_have_cmd = 1;
*g_ucUARTBuffer = 0x00;
__bic_SR_register_on_exit(LPM0_bits);
}
g_ucUARTBuffer++;
#endif
__no_operation();
break;
case 4:break; /* Vector 4 - TXIFG */
default: break;
}
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKIO);
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
P1DIR |= 0x01; // P1.0 output
TA1CTL = TASSEL_1 + MC_2 + TACLR + TAIE; // ACLK, contmode, clear TAR
// enable interrupt
__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1DIR |= BIT0; // P1.0/LED output direction
// Setup ComparatorB
CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0
CBCTL1 |= CBPWRMD_1; // normal power mode
CBCTL2 |= CBRSEL; // VREF is applied to -terminal
CBCTL2 |= CBRS_3+CBREFL_1; // R-ladder off; bandgap ref voltage (1.2V)
// supplied ref amplifier to get Vcref=1.5V (CBREFL_2)
CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0
__delay_cycles(75); // delay for the reference to settle
CBINT &= ~(CBIFG + CBIIFG); // Clear any errant interrupts
CBINT |= CBIE; // Enable CompB Interrupt on rising edge of CBIFG (CBIES=0)
CBCTL1 |= CBON; // Turn On ComparatorB
__bis_SR_register(LPM4_bits+GIE); // Enter LPM4 with inetrrupts enabled
__no_operation(); // For debug
}
__interrupt void USCI_B0_ISR(void)
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break; // Vector 0: No interrupts
case 2: break; // Vector 2: ALIFG
case 4: break; // Vector 4: NACKIFG
case 6: // Vector 6: STTIFG
UCB0IFG &= ~UCSTTIFG; // Clear start condition int flag
break;
case 8: // Vector 8: STPIFG
UCB0IFG &= ~UCSTPIFG; // Clear stop condition int flag
//__bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 if data was transmitted
break;
case 10: // Vector 10: RXIFG
command_mode = UCB0RXBUF; // Get RX data
if(command_mode==1){
//P1OUT |=BIT2;
senscan_Rtc.RTC_Serial[6] =(unsigned char)(CloCk_tick >> 8);
senscan_Rtc.RTC_Serial[7] =(unsigned char) CloCk_tick;
PTxData = (unsigned char *)senscan_Rtc.RTC_Serial ; // Start of TX buffer
}
if(command_mode==2){
P1OUT ^=BIT2;
PTxData = (unsigned char *)TxData2; // Start of TX buffer
}
break;
case 12: // Vector 12: TXIFG
UCB0TXBUF = *PTxData++; // Transmit data at address PTxData
break;
default:
__no_operation();
break;
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
MPY32CTL0 = MPYSAT+MPYC; // Saturation mode enable,
// Carry bit set
RES3 = 0;
RES2 = 0;
RES1 = 0x0000; // Pre-load first negative value
RES0 = 0x8000;
MACS = 0x8000; // Add to second negative value
OP2 = 0x05;
Result_upper16 = RESHI; // Result_upper15 = 0x8000
Result_lower16 = RESLO; // Result_lower15 = 0x0000
MPY32CTL0 &= ~MPYSAT; // Clear saturation mode
__bis_SR_register(LPM4_bits); // LPM4
__no_operation(); // For debugger
}
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
Port_Mapping();
// Setup Port Pins
P4DIR |= 0xFF; // P4.0 - P4.7 output
P4SEL |= 0xFF; // P4.0 - P4.6 Port Map functions
// Setup TB0
TB0CCR0 = 128; // PWM Period/2
TB0CCTL1 = OUTMOD_6; // CCR1 toggle/set
TB0CCR1 = 96; // CCR1 PWM duty cycle
TB0CCTL2 = OUTMOD_6; // CCR2 toggle/set
TB0CCR2 = 64; // CCR2 PWM duty cycle
TB0CCTL3 = OUTMOD_6; // CCR1 toggle/set
TB0CCR3 = 32; // CCR1 PWM duty cycle
TB0CTL = TBSSEL_1 + MC_3; // ACLK/2, up-down mode
__bis_SR_register(LPM3_bits); // Enter LPM3
__no_operation(); // For debugger
}