/*
* Set the executing CPUs power mode as defined. This will be in
* preparation for it executing a WFI instruction.
*
* This function must be called with preemption disabled, and as it
* has the side effect of disabling coherency, caches must have been
* flushed. Interrupts must also have been disabled.
*/
int scu_power_mode(void __iomem *scu_base, unsigned int mode)
{
unsigned int val;
int cpu = smp_processor_id();
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;
val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
val |= mode;
__raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
return 0;
}
static int max63xx_wdt_stop(struct watchdog_device *wdd)
{
u8 val;
spin_lock(&io_lock);
val = __raw_readb(wdt_base);
val &= ~MAX6369_WDSET;
val |= 3;
__raw_writeb(val, wdt_base);
spin_unlock(&io_lock);
return 0;
}
static int max63xx_wdt_ping(struct watchdog_device *wdd)
{
u8 val;
spin_lock(&io_lock);
val = __raw_readb(wdt_base);
__raw_writeb(val | MAX6369_WDI, wdt_base);
__raw_writeb(val & ~MAX6369_WDI, wdt_base);
spin_unlock(&io_lock);
return 0;
}
/*
* Set the executing CPUs power mode as defined. This will be in
* preparation for it executing a WFI instruction.
*
* This function must be called with preemption disabled, and as it
* has the side effect of disabling coherency, caches must have been
* flushed. Interrupts must also have been disabled.
*/
int scu_power_mode(void __iomem *scu_base, unsigned int mode)
{
unsigned int val;
int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;
val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
val |= mode;
__raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
return 0;
}
/* --- Management command API --- */
static int bm_mc_init(struct bm_portal *portal)
{
struct bm_mc *mc = &portal->mc;
mc->cr = portal->addr.ce + BM_CL_CR;
mc->rr = portal->addr.ce + BM_CL_RR0;
mc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & BM_MCC_VERB_VBIT) ?
0 : 1;
mc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = mc_idle;
#endif
return 0;
}
static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
int retval, dev, busno, func;
struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
void __iomem *cfgdata =
(void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
dev = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
/* check if the bus is top-level */
if (bus->parent != NULL)
busno = bus->number;
else {
busno = 0;
}
if (mkaddr(busno, devfn, where, pcicptr))
return -1;
switch (size) {
case 1:
#ifdef __BIG_ENDIAN
cfgdata += (where & 3) ^ 3;
#else
cfgdata += where & 3;
#endif
*val = __raw_readb(cfgdata);
break;
case 2:
#ifdef __BIG_ENDIAN
cfgdata += (where & 2) ^ 2;
#else
cfgdata += where & 2;
#endif
*val = __raw_readw(cfgdata);
break;
case 4:
*val = __raw_readl(cfgdata);
break;
}
retval = check_abort(pcicptr);
if (retval == PCIBIOS_DEVICE_NOT_FOUND)
*val = 0xffffffff;
return retval;
}
static void __init magician_init(void)
{
void __iomem *cpld;
int lcd_select;
int err;
gpio_request(GPIO13_MAGICIAN_CPLD_IRQ, "CPLD_IRQ");
gpio_request(GPIO107_MAGICIAN_DS1WM_IRQ, "DS1WM_IRQ");
pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
platform_add_devices(ARRAY_AND_SIZE(devices));
err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN");
if (!err) {
gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1);
pxa_set_ficp_info(&magician_ficp_info);
}
pxa27x_set_i2c_power_info(NULL);
pxa_set_i2c_info(&i2c_info);
pxa_set_mci_info(&magician_mci_info);
pxa_set_ohci_info(&magician_ohci_info);
/* Check LCD type we have */
cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000);
if (cpld) {
u8 board_id = __raw_readb(cpld+0x14);
iounmap(cpld);
system_rev = board_id & 0x7;
lcd_select = board_id & 0x8;
pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly");
if (lcd_select && (system_rev < 3)) {
gpio_request(GPIO75_MAGICIAN_SAMSUNG_POWER, "SAMSUNG_POWER");
gpio_direction_output(GPIO75_MAGICIAN_SAMSUNG_POWER, 0);
}
gpio_request(GPIO104_MAGICIAN_LCD_POWER_1, "LCD_POWER_1");
gpio_request(GPIO105_MAGICIAN_LCD_POWER_2, "LCD_POWER_2");
gpio_request(GPIO106_MAGICIAN_LCD_POWER_3, "LCD_POWER_3");
gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0);
gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0);
gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0);
set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info);
} else
pr_err("LCD detection: CPLD mapping failed\n");
}
static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
{
unsigned int val;
val = __raw_readb(BAST_VA_CTRL3);
printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
if (vpp)
val |= BAST_CPLD_CTRL3_ROMWEN;
else
val &= ~BAST_CPLD_CTRL3_ROMWEN;
__raw_writeb(val, BAST_VA_CTRL3);
}
static unsigned long gpio_read_raw_reg(unsigned long reg,
unsigned long reg_width)
{
switch (reg_width) {
case 8:
return __raw_readb(reg);
case 16:
return __raw_readw(reg);
case 32:
return __raw_readl(reg);
}
BUG();
return 0;
}
static void serial_wait_tx(void)
{
static const unsigned long uart_bases[3] = {
0x4806a000, 0x4806c000, 0x4806e000
};
unsigned long lsr_reg;
int looped = 0;
/* Wait for TX FIFO and THR to get empty */
lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
looped = 1;
if (looped)
serial_console_kick();
}
static inline u32 get_fpga_unmasked_irqs(void)
{
return
((__raw_readb(OMAP1510_FPGA_ISR_LO) &
__raw_readb(OMAP1510_FPGA_IMR_LO))) |
((__raw_readb(OMAP1510_FPGA_ISR_HI) &
__raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
((__raw_readb(INNOVATOR_FPGA_ISR2) &
__raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
}
static int v3_write_config_byte(struct pci_dev *dev, int where, u8 val)
{
unsigned long addr;
unsigned long flags;
spin_lock_irqsave(&v3_lock, flags);
addr = v3_open_config_window(dev, where);
__raw_writeb(val, addr);
__raw_readb(addr);
v3_close_config_window();
spin_unlock_irqrestore(&v3_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static int pca_gmi_readbyte(void *pd, int reg)
{
int res;
struct tegra_nor_chip_parms *chip_parm = info->plat;
struct cs_info *csinfo = &chip_parm->csinfo;
unsigned int *ptr = csinfo->virt;
struct gpio_state *state = &csinfo->gpio_cs;
snor_tegra_writel(info, info->init_config, TEGRA_SNOR_CONFIG_REG);
snor_tegra_writel(info, info->timing1_read, TEGRA_SNOR_TIMING1_REG);
snor_tegra_writel(info, info->timing0_read, TEGRA_SNOR_TIMING0_REG);
gpio_set_value(state[0].gpio_num, state[0].value);
res = __raw_readb(ptr + reg);
return res;
}
void memcpy_fromio(void *to, const volatile void __iomem *from, long count)
{
/*
*/
if (count >= 8 && ((u64)to & 7) == ((u64)from & 7)) {
count -= 8;
do {
*(u64 *)to = __raw_readq(from);
count -= 8;
to += 8;
from += 8;
} while (count >= 0);
count += 8;
}
if (count >= 4 && ((u64)to & 3) == ((u64)from & 3)) {
count -= 4;
do {
*(u32 *)to = __raw_readl(from);
count -= 4;
to += 4;
from += 4;
} while (count >= 0);
count += 4;
}
if (count >= 2 && ((u64)to & 1) == ((u64)from & 1)) {
count -= 2;
do {
*(u16 *)to = __raw_readw(from);
count -= 2;
to += 2;
from += 2;
} while (count >= 0);
count += 2;
}
while (count > 0) {
*(u8 *) to = __raw_readb(from);
count--;
to++;
from++;
}
mb();
}
static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
{
unsigned int tmp;
slot = set->nr_map[slot] & 3;
pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
slot, set, set->nr_map);
tmp = __raw_readb(ANUBIS_VA_CTRL1);
tmp &= ~ANUBIS_CTRL1_NANDSEL;
tmp |= slot;
pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}
/*
* Copy data from IO memory space to "real" memory space.
* This needs to be optimized.
*/
void memcpy_fromio(void *to, const volatile void __iomem *from, long count)
{
/* Optimize co-aligned transfers. Everything else gets handled
a byte at a time. */
if (count >= 8 && ((u64)to & 7) == ((u64)from & 7)) {
count -= 8;
do {
*(u64 *)to = __raw_readq(from);
count -= 8;
to += 8;
from += 8;
} while (count >= 0);
count += 8;
}
if (count >= 4 && ((u64)to & 3) == ((u64)from & 3)) {
count -= 4;
do {
*(u32 *)to = __raw_readl(from);
count -= 4;
to += 4;
from += 4;
} while (count >= 0);
count += 4;
}
if (count >= 2 && ((u64)to & 1) == ((u64)from & 1)) {
count -= 2;
do {
*(u16 *)to = __raw_readw(from);
count -= 2;
to += 2;
from += 2;
} while (count >= 0);
count += 2;
}
while (count > 0) {
*(u8 *) to = __raw_readb(from);
count--;
to++;
from++;
}
mb();
}
static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
unsigned int tmp;
slot = set->nr_map[slot] & 3;
pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
slot, set, set->nr_map);
tmp = __raw_readb(OSIRIS_VA_CTRL0);
tmp &= ~OSIRIS_CTRL0_NANDSEL;
tmp |= slot;
pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}
static void simtec_nor_vpp(struct map_info *map, int vpp)
{
unsigned int val;
unsigned long flags;
local_irq_save(flags);
val = __raw_readb(BAST_VA_CTRL3);
printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
if (vpp)
val |= BAST_CPLD_CTRL3_ROMWEN;
else
val &= ~BAST_CPLD_CTRL3_ROMWEN;
__raw_writeb(val, BAST_VA_CTRL3);
local_irq_restore(flags);
}
static void bast_flash_setrw(int to)
{
unsigned int val;
unsigned long flags;
local_irq_save(flags);
val = __raw_readb(BAST_VA_CTRL3);
if (to)
val |= BAST_CPLD_CTRL3_ROMWEN;
else
val &= ~BAST_CPLD_CTRL3_ROMWEN;
pr_debug("new cpld ctrl3=%02x\n", val);
__raw_writeb(val, BAST_VA_CTRL3);
local_irq_restore(flags);
}
static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
unsigned int tmp;
slot = set->nr_map[slot] & 3;
pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
slot, set, set->nr_map);
tmp = __raw_readb(BAST_VA_CTRL2);
tmp &= BAST_CPLD_CTLR2_IDERST;
tmp |= slot;
tmp |= BAST_CPLD_CTRL2_WNAND;
pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
__raw_writeb(tmp, BAST_VA_CTRL2);
}
static ssize_t gmichar_chrdev_read_helper(char *dest, int *src,
size_t size)
{
int i;
snor_tegra_writel(info, info->init_config, TEGRA_SNOR_CONFIG_REG);
snor_tegra_writel(info, info->timing1_read, TEGRA_SNOR_TIMING1_REG);
snor_tegra_writel(info, info->timing0_read, TEGRA_SNOR_TIMING0_REG);
udelay(1);
for (i = 0; i < size; i++)
dest[i] = __raw_readb(src + i);
udelay(1);
return size;
}
static map_word ichxrom_read(struct map_info *map, unsigned long ofs)
{
map_word val;
int i;
switch(map->bankwidth) {
case 1: val.x[0] = __raw_readb(addr(map, ofs)); break;
case 2: val.x[0] = __raw_readw(addr(map, ofs)); break;
case 4: val.x[0] = __raw_readl(addr(map, ofs)); break;
#if BITS_PER_LONG >= 64
case 8: val.x[0] = __raw_readq(addr(map, ofs)); break;
#endif
default: val.x[0] = 0; break;
}
for(i = 1; i < map_words(map); i++) {
val.x[i] = 0;
}
return val;
}
static void ts72xx_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
void __iomem *addr = chip->IO_ADDR_R;
unsigned char bits;
addr += (1 << TS72XX_NAND_CONTROL_ADDR_LINE);
bits = __raw_readb(addr) & ~0x07;
bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */
bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */
bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */
__raw_writeb(bits, addr);
}
static void events_import_bits(struct event_dev *edev, unsigned long bits[], unsigned type, size_t count)
{
int i, j;
size_t size;
uint8_t val;
void __iomem *addr = edev->addr;
__raw_writel(PAGE_EVBITS | type, addr + REG_SET_PAGE);
size = __raw_readl(addr + REG_LEN) * 8;
if (size < count)
count = size;
addr = addr + REG_DATA;
for (i = 0; i < count; i += 8) {
val = __raw_readb(addr++);
for (j = 0; j < 8; j++)
if(val & 1 << j)
set_bit(i + j, bits);
}
}
/* until it's enabled, this UDC should be completely invisible
* to any USB host.
*/
static int udc_enable(struct elfin_udc *dev)
{
u32 val;
DPRINTK("%s, %p\n", __FUNCTION__, dev);
dev->gadget.speed = USB_SPEED_UNKNOWN;
val = usb_read(s3c24xx_misccr, 0);
val &= ~((1<<3)|(1<<13)); // USB Device in Normal mode
usb_write(val, s3c24xx_misccr, 0);
val = __raw_readb(S3C2410_CLKSLOW);
val &= ~S3C2410_CLKSLOW_USB_CLK_DISABLE; /* enable usb device clock */
__raw_writeb(val, S3C2410_CLKSLOW);
/* Enable Clock */
udc_clock = clk_get(NULL, "usb-device");
if (!udc_clock) {
printk("failed to get udc clock source\n");
return -ENOENT;
}
clk_use(udc_clock);
clk_enable(udc_clock);
val = (1<<0);
usb_write(val, S3C2410_UDC_EP_INT_REG, 0); //clear
val = (1<<2); //UD_USBINTE_RESET
usb_write(val, S3C2410_UDC_USB_INT_REG, 0); //clear
/* Set MAXP values for each */
usb_write(dev->ep[0].ep.maxpacket>>3, S3C2410_UDC_MAXP_REG, 0);
usb_write(dev->ep[1].ep.maxpacket>>3, S3C2410_UDC_MAXP_REG, 1);
usb_write(dev->ep[2].ep.maxpacket>>3, S3C2410_UDC_MAXP_REG, 2);
usb_write(dev->ep[3].ep.maxpacket>>3, S3C2410_UDC_MAXP_REG, 3);
usb_write(dev->ep[4].ep.maxpacket>>3, S3C2410_UDC_MAXP_REG, 4);
return 0;
}
static int osiris_pm_suspend(void)
{
unsigned int tmp;
pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
/* ensure correct NAND slot is selected on resume */
if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
tmp |= 2;
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
/* ensure that an nRESET is not generated on resume. */
s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
return 0;
}
static int max63xx_wdt_start(struct watchdog_device *wdd)
{
struct max63xx_timeout *entry = watchdog_get_drvdata(wdd);
u8 val;
spin_lock(&io_lock);
val = __raw_readb(wdt_base);
val &= ~MAX6369_WDSET;
val |= entry->wdset;
__raw_writeb(val, wdt_base);
spin_unlock(&io_lock);
/* check for a edge triggered startup */
if (entry->tdelay == 0)
max63xx_wdt_ping(wdd);
return 0;
}
static void hp6x0_apm_get_power_status(struct apm_power_info *info)
{
int battery, backup, charging, percentage;
u8 pgdr;
battery = adc_single(ADC_CHANNEL_BATTERY);
backup = adc_single(ADC_CHANNEL_BACKUP);
charging = adc_single(ADC_CHANNEL_CHARGE);
percentage = 100 * (battery - HP680_BATTERY_MIN) /
(HP680_BATTERY_MAX - HP680_BATTERY_MIN);
/* % of full battery */
info->battery_life = percentage;
/* We want our estimates in minutes */
info->units = 0;
/* Extremely(!!) rough estimate, we will replace this with a datalist later on */
info->time = (2 * battery);
info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ?
APM_AC_ONLINE : APM_AC_OFFLINE;
pgdr = __raw_readb(PGDR);
if (pgdr & PGDR_MAIN_BATTERY_OUT) {
info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
info->battery_flag = 0x80;
} else if (charging < 8) {
info->battery_status = APM_BATTERY_STATUS_CHARGING;
info->battery_flag = 0x08;
info->ac_line_status = 0x01;
} else if (percentage <= APM_CRITICAL) {
info->battery_status = APM_BATTERY_STATUS_CRITICAL;
info->battery_flag = 0x04;
} else if (percentage <= APM_LOW) {
info->battery_status = APM_BATTERY_STATUS_LOW;
info->battery_flag = 0x02;
} else {
info->battery_status = APM_BATTERY_STATUS_HIGH;
info->battery_flag = 0x01;
}
}
static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
{
unsigned int tmp;
pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
/* ensure correct NAND slot is selected on resume */
if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
tmp |= 2;
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
/* ensure that an nRESET is not generated on resume. */
s3c2410_gpio_setpin(S3C2410_GPA21, 1);
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
return 0;
}
static int osiris_pm_suspend(void)
{
unsigned int tmp;
pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
/* ensure correct NAND slot is selected on resume */
if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
tmp |= 2;
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
/* ensure that an nRESET is not generated on resume. */
gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
gpio_free(S3C2410_GPA(21));
return 0;
}