inline unsigned int read_pmc(unsigned int pmc)
{
switch (pmc) {
default:
case 0:
return __read_32bit_c0_register($25, 1);
case 1:
return __read_32bit_c0_register($25, 3);
}
}
trace_t *TRACE_NEXT(trace_types_t trace_type)
{
trace_t *p;
p = traces + trace_next;
#if defined(CONFIG_ARCH_SA1100) || \
defined (CONFIG_ARCH_PXA)
p->oscr = OSCR;
#elif defined(CONFIG_SOC_AU1X00) || \
defined(CONFIG_MIPS_AU1X00) || \
defined(CONFIG_CPU_AU1X00) || \
defined(CONFIG_MIPS_AU1000) || \
defined(CONFIG_MIPS_PB1500) || \
defined(CONFIG_MIPS_PB1100)
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19)
p->cp0_count = __read_32bit_c0_register(CP0_COUNT);
#else
p->cp0_count = read_c0_count();
#endif
#elif defined(CONFIG_ARCH_SAMSUNG)
p->tcnt1 = *(volatile u32 *)TCNT1;
#else
p->jiffies = jiffies;
#endif
#if defined(CONFIG_SOC_AU1X00) || \
defined(CONFIG_MIPS_AU1X00) || \
defined(CONFIG_CPU_AU1X00) || \
defined(CONFIG_MIPS_AU1000) || \
defined(CONFIG_MIPS_PB1500) || \
defined(CONFIG_MIPS_PB1100)
//p->sofs = au_readl(USBD_FRAMENUM);
#endif
#if defined(CONFIG_ARCH_MX1ADS)
p->sofs = USBD_FRAME & 0x3ff;
#endif
p->interrupts = udc_interrupts;
p->trace_type = trace_type;
trace_next++;
trace_next = (trace_next == TRACE_MAX) ? 0 : trace_next;
if (trace_next == trace_first) {
trace_first++;
trace_first = (trace_first == TRACE_MAX) ? 0 : trace_first;
}
return p;
}
void __init cfe_die(char *fmt, ...)
{
char msg[128];
va_list ap;
int handle;
unsigned int count;
va_start(ap, fmt);
vsprintf(msg, fmt, ap);
strcat(msg, "\r\n");
if (cfe_seal != CFE_EPTSEAL)
goto no_cfe;
/* disable XKS01 so that CFE can access the registers */
#if defined(CONFIG_BMIPS4380)
__write_32bit_c0_register($22, 3,
__read_32bit_c0_register($22, 3) & ~BIT(12));
#elif defined(CONFIG_BMIPS5000)
__write_32bit_c0_register($22, 5,
__read_32bit_c0_register($22, 5) & ~BIT(8));
#endif
handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
if (handle < 0)
goto no_cfe;
cfe_write(handle, msg, strlen(msg));
for (count = 0; count < 0x7fffffff; count++)
mb();
cfe_exit(0, 1);
while (1)
;
no_cfe:
/* probably won't print anywhere useful */
printk(KERN_ERR "%s", msg);
BUG();
va_end(ap);
}
void __init plat_mem_setup(void)
{
extern int panic_timeout;
#ifdef CONFIG_MIPS_BRCM
#if defined( CONFIG_MIPS_BCM7038A0 )
set_io_port_base(0xe0000000); /* start of PCI IO space. */
#elif defined( CONFIG_MIPS_BCM7038B0 ) || defined( CONFIG_MIPS_BCM7038C0 ) \
|| defined( CONFIG_MIPS_BCM7400 ) || defined( CONFIG_MIPS_BCM3560 ) \
|| defined( CONFIG_MIPS_BCM7401 ) || defined( CONFIG_MIPS_BCM7402 ) \
|| defined( CONFIG_MIPS_BCM7118 ) \
|| defined( CONFIG_MIPS_BCM7403 ) || defined( CONFIG_MIPS_BCM7405 ) \
|| defined( CONFIG_MIPS_BCM7335 ) || defined( CONFIG_MIPS_BCM7325 ) \
|| defined( CONFIG_MIPS_BCM3548 ) || defined( CONFIG_MIPS_BCM7420 ) \
|| defined( CONFIG_MIPS_BCM7336 ) || defined( CONFIG_MIPS_BCM7340 )
set_io_port_base(0xf0000000); /* start of PCI IO space. */
#elif defined( CONFIG_MIPS_BCM7329 )
set_io_port_base(KSEG1ADDR(0x1af90000));
#elif defined ( CONFIG_BCM93730 )
set_io_port_base(KSEG1ADDR(0x13000000));
#elif defined( CONFIG_MIPS_BCM7440 ) || defined (CONFIG_MIPS_BCM7601) || defined (CONFIG_MIPS_BCM7635)
set_io_port_base(PCI_IO_WIN_BASE); /* 0xf8000000 in boardmap.h. */
#else
set_io_port_base(0);
#endif
#endif
_machine_restart = brcm_machine_restart;
_machine_halt = brcm_machine_halt;
//_machine_power_off = brcm_machine_power_off;
pm_power_off = brcm_machine_power_off;
board_time_init = brcm_time_init;
panic_timeout = 180;
#if defined( CONFIG_MIPS_BCM7440B0 ) || defined( CONFIG_MIPS_BCM7325B0 ) \
|| defined( CONFIG_MIPS_BCM7443A0 ) || defined (CONFIG_MIPS_BCM7601) \
|| defined( CONFIG_MIPS_BCM7635A0 )
// Set externalize IO sync bit (CP0 $16, sel 7, bit 8)
{
uint32_t extIO = __read_32bit_c0_register($16, 7);
__write_32bit_c0_register($16, 7, extIO | 0x100);
extIO = __read_32bit_c0_register($16, 7);
}
#endif
#ifdef CONFIG_PC_KEYB
kbd_ops = &brcm_kbd_ops;
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_DISCONTIGMEM
brcm_numa_init();
#endif
}
void __init plat_mem_setup(void)
{
extern int rac_setting(int);
extern int panic_timeout;
#ifdef CONFIG_MIPS_BRCM
#if defined( CONFIG_MIPS_BCM7038A0 )
set_io_port_base(0xe0000000); /* start of PCI IO space. */
#elif defined( CONFIG_MIPS_BCM7038B0 ) || defined( CONFIG_MIPS_BCM7038C0 ) \
|| defined( CONFIG_MIPS_BCM7400 ) || defined( CONFIG_MIPS_BCM3560 ) \
|| defined( CONFIG_MIPS_BCM7401 ) || defined( CONFIG_MIPS_BCM7402 ) \
|| defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7440 ) \
|| defined( CONFIG_MIPS_BCM7403 ) || defined( CONFIG_MIPS_BCM7405 ) \
|| defined( CONFIG_MIPS_BCM7335 ) || defined( CONFIG_MIPS_BCM7325 ) \
|| defined( CONFIG_MIPS_BCM3548 )
set_io_port_base(0xf0000000); /* start of PCI IO space. */
#elif defined( CONFIG_MIPS_BCM7329 )
set_io_port_base(KSEG1ADDR(0x1af90000));
#elif defined ( CONFIG_BCM93730 )
set_io_port_base(KSEG1ADDR(0x13000000));
#else
set_io_port_base(0);
#endif
#endif
#ifndef CONFIG_TIVO
_machine_restart = brcm_machine_restart;
_machine_halt = brcm_machine_halt;
//_machine_power_off = brcm_machine_power_off;
pm_power_off = brcm_machine_power_off;
board_time_init = brcm_time_init;
panic_timeout = 180;
#else
_machine_restart = (void(*)(char *))tivo_machine_restart;
_machine_halt = tivo_machine_restart;
pm_power_off = tivo_machine_restart;
board_time_init = brcm_time_init;
panic_timeout = 3;
#endif
// Set RAC on 7400
#if defined( CONFIG_MIPS_BCM7400A0 )
rac_setting(1);
#endif
#if defined( CONFIG_MIPS_BCM7440B0 ) || defined( CONFIG_MIPS_BCM7325A0 ) \
|| defined( CONFIG_MIPS_BCM7443A0 )
// Set externalize IO sync bit (CP0 $16, sel 7, bit 8)
{
uint32_t extIO = __read_32bit_c0_register($16, 7);
__write_32bit_c0_register($16, 7, extIO | 0x100);
extIO = __read_32bit_c0_register($16, 7);
}
#endif
#ifdef CONFIG_PC_KEYB
kbd_ops = &brcm_kbd_ops;
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_DISCONTIGMEM
brcm_numa_init();
#endif
}
void nlm_common_oprofile_int_handler(int irq, void * dev_id,
struct pt_regs *regs)
{
uint32_t counter1, counter2;
uint32_t control1, control2;
int i;
int cpu_id = netlogic_cpu_id() * 4; /* 0, 4, 8 ... 28 */
int h_id = hard_smp_processor_id();/* 0, 1, 2, 3, 4, .....31 */
int ret, lcpu;
int sample1_taken=0;
int sample2_taken=0;
extern struct plat_smp_ops *mp_ops;
if(g_stop_pmc[h_id])
return;
if(((ret = nlm_common_pmc_owner_nolock()) == 0)) {
/* if any counter overflow occured on this core.... */
if(nlm_common_pc_of_mask1[h_id]) {
oprofile_add_sample(regs, 0);
}
if(nlm_common_pc_of_mask2[h_id]) {
oprofile_add_sample(regs, 1);
}
return;
}
control1 = __read_32bit_c0_register ($25, 0);
control2 = __read_32bit_c0_register ($25, 2);
counter1 = __read_32bit_c0_register ($25, 1);
counter2 = __read_32bit_c0_register ($25, 3);
if (((int)counter1) < 0) {
__write_32bit_c0_register($25, 0, 0);
oprofile_add_sample(regs, 0);
counter1 = reg.reset_counter[0];
sample1_taken = 1;
for(i=0; i < 4; i++)
nlm_common_pc_of_mask1[cpu_id + i] = 1;
wmb();
for(i=1; i < 4; i++) {
lcpu = cpu_number_map(cpu_id+i);
if(lcpu && cpu_isset(lcpu, cpu_online_map)) {
mp_ops->send_ipi_single(lcpu, SMP_OPROFILE_IPI);
}
}
}
if (((int)counter2) < 0) {
__write_32bit_c0_register($25, 2, 0);
oprofile_add_sample(regs, 1);
counter2 = reg.reset_counter[1];
sample2_taken = 1;
for(i=0; i < 4; i++)
nlm_common_pc_of_mask2[cpu_id + i] = 1;
wmb();
for(i=1; i < 4; i++) {
lcpu = cpu_number_map(cpu_id+i);
if(lcpu && cpu_isset(lcpu, cpu_online_map)) {
mp_ops->send_ipi_single(lcpu, SMP_OPROFILE_IPI);
}
}
}
if(sample1_taken) {
__write_32bit_c0_register($25, 1, counter1);
__write_32bit_c0_register($25, 0, reg.control[0]);
}
if(sample2_taken) {
__write_32bit_c0_register($25, 3, counter2);
__write_32bit_c0_register($25, 2, reg.control[1]);
}
return ;
}
