void __init configure_sr_hpm_lp_pll(struct pll_config *config, struct pll_config_regs *regs, u32 ena_fsm_mode) { __configure_pll(config, regs, ena_fsm_mode); if (ena_fsm_mode) __set_fsm_mode(PLL_MODE_REG(regs), 0x1, 0x0); }
static void __init_alpha_pll(struct clk *c) { struct alpha_pll_clk *pll = to_alpha_pll_clk(c); struct alpha_pll_masks *masks = pll->masks; u32 regval; if (masks->output_mask && pll->enable_config) { regval = readl_relaxed(OUTPUT_REG(pll)); regval &= ~masks->output_mask; regval |= pll->enable_config; writel_relaxed(regval, OUTPUT_REG(pll)); } if (masks->post_div_mask) { regval = readl_relaxed(USER_CTL_LO_REG(pll)); regval &= ~masks->post_div_mask; regval |= pll->post_div_config; writel_relaxed(regval, USER_CTL_LO_REG(pll)); } if (pll->slew) { regval = readl_relaxed(USER_CTL_HI_REG(pll)); regval &= ~PLL_LATCH_INTERFACE; writel_relaxed(regval, USER_CTL_HI_REG(pll)); } if (masks->config_ctl_mask) { regval = readl_relaxed(CFG_CTL_REG(pll)); regval &= ~masks->config_ctl_mask; regval |= pll->config_ctl_val; writel_relaxed(regval, CFG_CTL_REG(pll)); } if (masks->test_ctl_lo_mask) { regval = readl_relaxed(TEST_CTL_LO_REG(pll)); regval &= ~masks->test_ctl_lo_mask; regval |= pll->test_ctl_lo_val; writel_relaxed(regval, TEST_CTL_LO_REG(pll)); } if (masks->test_ctl_hi_mask) { regval = readl_relaxed(TEST_CTL_HI_REG(pll)); regval &= ~masks->test_ctl_hi_mask; regval |= pll->test_ctl_hi_val; writel_relaxed(regval, TEST_CTL_HI_REG(pll)); } if (pll->fsm_en_mask) __set_fsm_mode(MODE_REG(pll)); pll->inited = true; }
void configure_pll(struct pll_config *config, struct pll_config_regs *regs, u32 ena_fsm_mode) { u32 regval; writel_relaxed(config->l, PLL_L_REG(regs)); writel_relaxed(config->m, PLL_M_REG(regs)); writel_relaxed(config->n, PLL_N_REG(regs)); regval = readl_relaxed(PLL_CONFIG_REG(regs)); /* Enable the MN accumulator */ if (config->mn_ena_mask) { regval &= ~config->mn_ena_mask; regval |= config->mn_ena_val; } /* Enable the main output */ if (config->main_output_mask) { regval &= ~config->main_output_mask; regval |= config->main_output_val; } /* Set pre-divider and post-divider values */ regval &= ~config->pre_div_mask; regval |= config->pre_div_val; regval &= ~config->post_div_mask; regval |= config->post_div_val; /* Select VCO setting */ regval &= ~config->vco_mask; regval |= config->vco_val; writel_relaxed(regval, PLL_CONFIG_REG(regs)); /* Configure in FSM mode if necessary */ if (ena_fsm_mode) __set_fsm_mode(PLL_MODE_REG(regs)); }
void __init configure_pll(struct pll_config *config, struct pll_config_regs *regs, u32 ena_fsm_mode) { u32 regval; writel_relaxed(config->l, PLL_L_REG(regs)); writel_relaxed(config->m, PLL_M_REG(regs)); writel_relaxed(config->n, PLL_N_REG(regs)); regval = readl_relaxed(PLL_CONFIG_REG(regs)); if (config->mn_ena_mask) { regval &= ~config->mn_ena_mask; regval |= config->mn_ena_val; } if (config->main_output_mask) { regval &= ~config->main_output_mask; regval |= config->main_output_val; } regval &= ~config->pre_div_mask; regval |= config->pre_div_val; regval &= ~config->post_div_mask; regval |= config->post_div_val; regval &= ~config->vco_mask; regval |= config->vco_val; writel_relaxed(regval, PLL_CONFIG_REG(regs)); if (ena_fsm_mode) __set_fsm_mode(PLL_MODE_REG(regs)); }