static int variable_rate_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
int ret = 0, count;
u32 mode, testlo;
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
u32 mode_lock;
u64 time;
bool early_lock = false;
spin_lock_irqsave(&pll_reg_lock, flags);
if (unlikely(!to_pll_clk(c)->inited))
__variable_rate_pll_init(c);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* Set test control bits as required by HW doc */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(pll->vals.test_ctl_lo_val,
PLL_TEST_CTL_LO_REG(pll));
/* Enable test_ctl debug */
mode |= BIT(3);
writel_relaxed(mode, PLL_MODE_REG(pll));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0xC0;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Use 10us to be sure.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* 5us delay mandated by HPG. However, put in a 200us delay here.
* This is to address possible locking issues with the PLL exhibit
* early "transient" locks about 16us from this point. With this
* higher delay, we avoid running into those transients.
*/
mb();
udelay(200);
/* Clear test control bits */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(0x0, PLL_TEST_CTL_LO_REG(pll));
time = sched_clock();
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask) {
udelay(1);
/*
* Check again to be sure. This is to avoid
* breaking too early if there is a "transient"
* lock.
*/
if ((readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
break;
else
early_lock = true;
}
udelay(1);
}
time = sched_clock() - time;
mode_lock = readl_relaxed(PLL_STATUS_REG(pll));
if (!(mode_lock & lockmask)) {
pr_err("PLL lock bit detection total wait time: %lld ns", time);
pr_err("PLL %s didn't lock after enabling for L value 0x%x!\n",
c->dbg_name, readl_relaxed(PLL_L_REG(pll)));
pr_err("mode register is 0x%x\n",
readl_relaxed(PLL_STATUS_REG(pll)));
pr_err("user control register is 0x%x\n",
readl_relaxed(PLL_CONFIG_REG(pll)));
pr_err("config control register is 0x%x\n",
readl_relaxed(PLL_CFG_CTL_REG(pll)));
pr_err("test control high register is 0x%x\n",
readl_relaxed(PLL_TEST_CTL_HI_REG(pll)));
pr_err("test control low register is 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)));
pr_err("early lock? %s\n", early_lock ? "yes" : "no");
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0x40;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0x80;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
testlo = readl_relaxed(PLL_TEST_CTL_LO_REG(pll));
testlo &= ~BM(7, 6);
testlo |= 0xC0;
writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));
/* Wait for the write to complete */
mb();
pr_err("test_ctl_lo = 0x%x, pll status is: 0x%x\n",
readl_relaxed(PLL_TEST_CTL_LO_REG(pll)),
readl_relaxed(PLL_ALT_STATUS_REG(pll)));
panic("failed to lock %s PLL\n", c->dbg_name);
}
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
static int variable_rate_pll_clk_enable(struct clk *c)
{
unsigned long flags;
struct pll_clk *pll = to_pll_clk(c);
int ret = 0, count;
u32 mode;
u32 lockmask = pll->masks.lock_mask ?: PLL_LOCKED_BIT;
spin_lock_irqsave(&pll_reg_lock, flags);
if (unlikely(!to_pll_clk(c)->inited))
__variable_rate_pll_init(c);
mode = readl_relaxed(PLL_MODE_REG(pll));
/* Set test control bits as required by HW doc */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(pll->vals.test_ctl_lo_val,
PLL_TEST_CTL_LO_REG(pll));
/* Disable PLL bypass mode. */
mode |= PLL_BYPASSNL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Use 10us to be sure.
*/
mb();
udelay(10);
/* De-assert active-low PLL reset. */
mode |= PLL_RESET_N;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* 5us delay mandated by HPG. Use 10 to be sure. */
mb();
udelay(10);
/* Clear test control bits */
if (pll->test_ctl_lo_reg && pll->vals.test_ctl_lo_val &&
pll->pgm_test_ctl_enable)
writel_relaxed(0x0, PLL_TEST_CTL_LO_REG(pll));
/* Wait for pll to lock. */
for (count = ENABLE_WAIT_MAX_LOOPS; count > 0; count--) {
if (readl_relaxed(PLL_STATUS_REG(pll)) & lockmask)
break;
udelay(1);
}
if (!(readl_relaxed(PLL_STATUS_REG(pll)) & lockmask))
pr_err("PLL %s didn't lock after enabling it!\n", c->dbg_name);
/* Enable PLL output. */
mode |= PLL_OUTCTRL;
writel_relaxed(mode, PLL_MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
spin_unlock_irqrestore(&pll_reg_lock, flags);
return ret;
}
