/*
* Jump to reset vector.
*/
void
cpu_reset()
{
_cpu_exception_suspend();
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
#ifndef __lint__
goto *(void *)0xa0000000;
#endif
/* NOTREACHED */
}
void
machine_reset(void)
{
_cpu_exception_suspend();
_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
(void)*(volatile uint32_t *)0x80000001; /* CPU shutdown */
/*NOTREACHED*/
for (;;) {
continue;
}
}
void
sh_clock_init(int flags, struct rtc_ops *rtc)
{
uint32_t s, t0, cnt_1s;
sh_clock.flags = flags;
if (rtc != NULL)
sh_clock.rtc = *rtc; /* structure copy */
/* Initialize TMU */
_reg_write_2(SH_(TCR0), 0);
_reg_write_2(SH_(TCR1), 0);
_reg_write_2(SH_(TCR2), 0);
/* Reset RTC alarm and interrupt */
_reg_write_1(SH_(RCR1), 0);
/* Stop all counter */
_reg_write_1(SH_(TSTR), 0);
/*
* Estimate CPU clock.
*/
if (sh_clock.flags & SH_CLOCK_NORTC) {
/* Set TMU channel 0 source to PCLOCK / 16 */
_reg_write_2(SH_(TCR0), TCR_TPSC_P16);
sh_clock.tmuclk = sh_clock.pclock / 16;
} else {
/* Set TMU channel 0 source to RTC counter clock (16.384kHz) */
_reg_write_2(SH_(TCR0),
CPU_IS_SH3 ? SH3_TCR_TPSC_RTC : SH4_TCR_TPSC_RTC);
sh_clock.tmuclk = SH_RTC_CLOCK;
/* Make sure RTC oscillator is enabled */
_reg_bset_1(SH_(RCR2), SH_RCR2_ENABLE);
}
s = _cpu_exception_suspend();
_cpu_spin(1); /* load function on cache. */
TMU_START(0);
_cpu_spin(10000000);
t0 = TMU_ELAPSED(0);
_cpu_exception_resume(s);
sh_clock.cpucycle_1us = (sh_clock.tmuclk * 10) / t0;
cnt_1s = ((uint64_t)sh_clock.tmuclk * 10000000 * 10 + t0 / 2) / t0;
if (CPU_IS_SH4)
sh_clock.cpuclock = cnt_1s / 2; /* two-issue */
else
sh_clock.cpuclock = cnt_1s;
/*
* Estimate PCLOCK
*/
if (sh_clock.pclock == 0) {
uint32_t t1;
/* set TMU channel 1 source to PCLOCK / 4 */
_reg_write_2(SH_(TCR1), TCR_TPSC_P4);
s = _cpu_exception_suspend();
_cpu_spin(1); /* load function on cache. */
TMU_START(0);
TMU_START(1);
_cpu_spin(cnt_1s); /* 1 sec. */
t0 = TMU_ELAPSED(0);
t1 = TMU_ELAPSED(1);
_cpu_exception_resume(s);
sh_clock.pclock =
((uint64_t)t1 * 4 * SH_RTC_CLOCK + t0 / 2) / t0;
}
/* Stop all counters */
_reg_write_1(SH_(TSTR), 0);
#undef TMU_START
#undef TMU_ELAPSED
}
