uint_32 _bsp_enable_card
(
void
)
{ /* Body */
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
_GET_KERNEL_DATA(kernel_data);
/* Set the CPU type */
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
#if MQX_EXIT_ENABLED
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
#endif
/* Initialize the MCF51CN support functions */
_mcf51EM_initialize_support(0);
/*
** Initialize the interrupt handling
*/
/* Mask all interrupts */
_mcf51EM_int_mask_all();
_int_set_vector_table(BSP_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED,
BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR,
(void (_CODE_PTR_)(pointer))_bsp_timer_isr, NULL) == NULL)
{
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
kernel_data->TIMER_HW_REFERENCE = _mcf51EM_timer_init_freq(BSP_TIMER,
BSP_BUS_CLOCK / BSP_ALARM_FREQUENCY, FALSE);
_time_set_hwtick_function(_bsp_get_hwticks,
(pointer)kernel_data->TIMER_HW_REFERENCE);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_mcf51EM_timer_unmask_int(BSP_TIMER);
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
/* Initialize RTC and MQX time */
#if BSPCFG_ENABLE_RTCDEV
_bsp_rtc_io_init ();
_rtc_sync_with_mqx (TRUE);
#endif
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/* Initialize the I/O Sub-system */
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
_mcf51xx_sci_polled_install("ttya:", &_bsp_sci0_init,
_bsp_sci0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYB
_mcf51xx_sci_polled_install("ttyb:", &_bsp_sci1_init,
_bsp_sci1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYC
_mcf51xx_sci_polled_install("ttyc:", &_bsp_sci2_init,
_bsp_sci2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYA
_mcf51xx_sci_int_install("ittya:", &_bsp_sci0_init,
_bsp_sci0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYB
_mcf51xx_sci_int_install("ittyb:", &_bsp_sci1_init,
_bsp_sci1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYC
_mcf51xx_sci_int_install("ittyc:", &_bsp_sci2_init,
_bsp_sci2_init.QUEUE_SIZE);
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
#if BSPCFG_ENABLE_I2C0
_mcf51xx_i2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C0
_mcf51xx_i2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
/* Install the GPIO driver */
#if BSPCFG_ENABLE_GPIODEV
_io_gpio_install("gpio:");
#endif
/* Install the LCD driver */
#if BSPCFG_ENABLE_LCD
_bsp_lcd_io_init();
#endif
/* Install ADC driver */
#if BSPCFG_ENABLE_ADC1
_io_adc_install("adc1:", &_bsp_adc1_init);
#endif
#if BSPCFG_ENABLE_ADC2
_io_adc_install("adc2:", &_bsp_adc2_init);
#endif
#if BSPCFG_ENABLE_ADC3
_io_adc_install("adc3:", &_bsp_adc3_init);
#endif
#if BSPCFG_ENABLE_ADC4
_io_adc_install("adc4:", &_bsp_adc4_init);
#endif
#if BSPCFG_ENABLE_SPI0
_mcf5xxx_spi16_polled_install("spi0:", &_bsp_spi0_init);
#endif
#if BSPCFG_ENABLE_ISPI0
_mcf5xxx_spi16_int_install("ispi0:", &_bsp_spi0_init);
#endif
#if BSPCFG_ENABLE_SPI1
_mcf5xxx_spi8_polled_install("spi1:", &_bsp_spi1_init);
#endif
#if BSPCFG_ENABLE_ISPI1
_mcf5xxx_spi8_int_install("ispi1:", &_bsp_spi1_init);
#endif
#if BSPCFG_ENABLE_SPI2
_mcf5xxx_spi8_polled_install("spi2:", &_bsp_spi2_init);
#endif
#if BSPCFG_ENABLE_ISPI2
_mcf5xxx_spi8_int_install("ispi2:", &_bsp_spi2_init);
#endif
/* install internal flash */
/* FLASHX1 array1 always start at address 0x00 to 0x1FFFF */
#if BSPCFG_ENABLE_FLASHX1
_mcf51em_internal_flash_array1_install("flashx1:", BSPCFG_FLASHX_SIZE1);
#endif
/* FLASHX2 array2 always start at address 0x20000 to 0x3FFFF */
#if BSPCFG_ENABLE_FLASHX2
_mcf51em_internal_flash_array2_install("flashx2:", BSPCFG_FLASHX_SIZE2);
#endif
#endif
return MQX_OK;
} /* Endbody */
/*!
* \cond DOXYGEN_PRIVATE
* \brief Pre initialization - initializing requested modules for basic run of MQX.
*/
int _bsp_pre_init(void)
{
uint32_t result;
/******************************************************************************
Init gpio platform pins for LEDs, setup board clock source
******************************************************************************/
/* Macro PEX_MQX_KSDK used by PEX team */
#ifndef PEX_MQX_KSDK
hardware_init();
/* Configure PINS for default UART instance */
#if defined(BOARD_USE_LPSCI)
configure_lpsci_pins(BOARD_DEBUG_UART_INSTANCE);
#elif defined(BOARD_USE_LPUART)
configure_lpuart_pins(BOARD_DEBUG_UART_INSTANCE);
#elif defined(BOARD_USE_UART)
configure_uart_pins(BOARD_DEBUG_UART_INSTANCE);
#else
#error Default serial module is unsupported or undefined.
#endif
#endif
#if MQX_EXIT_ENABLED
extern void _bsp_exit_handler(void);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
#endif
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
}
/******************************************************************************
Init MQX tick timer
******************************************************************************/
/* Initialize , set and run system hwtimer */
result = HWTIMER_SYS_Init(&systimer, &BSP_SYSTIMER_DEV, BSP_SYSTIMER_ID, NULL);
if (kStatus_OSA_Success != result) {
return MQX_INVALID_POINTER;
}
/* Set isr for timer*/
if (NULL == OSA_InstallIntHandler(BSP_SYSTIMER_INTERRUPT_VECTOR, HWTIMER_SYS_SystickIsrAction))
{
return kHwtimerRegisterHandlerError;
}
/* Set interrupt priority */
NVIC_SetPriority(BSP_SYSTIMER_INTERRUPT_VECTOR, MQX_TO_NVIC_PRIOR(BSP_SYSTIMER_ISR_PRIOR));
/* Disable interrupts to ensure ticks are not active until call of _sched_start_internal */
_int_disable();
result = HWTIMER_SYS_SetPeriod(&systimer, BSP_ALARM_PERIOD);
if (kStatus_OSA_Success != result) {
HWTIMER_SYS_Deinit(&systimer);
return MQX_INVALID_POINTER;
}
result = HWTIMER_SYS_RegisterCallback(&systimer,(hwtimer_callback_t)_time_notify_kernel, NULL);
if (kStatus_OSA_Success != result) {
HWTIMER_SYS_Deinit(&systimer);
return MQX_INVALID_POINTER;
}
result = HWTIMER_SYS_Start(&systimer);
if (kStatus_OSA_Success != result) {
HWTIMER_SYS_Deinit(&systimer);
return MQX_INVALID_POINTER;
}
/* Initialize the system ticks */
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_time_set_hwticks_per_tick(HWTIMER_SYS_GetModulo(&systimer));
_time_set_hwtick_function(_bsp_get_hwticks, (void *)NULL);
return MQX_OK;
}
/** Pre initialization - initializing requested modules for basic run of MQX.
*/
int _bsp_pre_init(void) {
KERNEL_DATA_STRUCT_PTR kernel_data;
uint32_t result;
_mqx_int i;
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MCF548x support functions */
_mcf5441_initialize_support(0);
/*
** Initialize the interrupt handling
*/
_int_set_vector_table(BSP_RAM_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR, _bsp_timer_isr, NULL) == NULL) {
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
#if BSPCFG_HAS_SRAM_POOL
/* When kernel data is placed outside of the SRAM memory create new _BSP_sram_pool in the SRAM,
otherwise if kernel data points to SRAM, the _BSP_sram_pool points to system pool. */
if ( (((uint32_t)__INTERNAL_SRAM_BASE) < (uint32_t)BSP_DEFAULT_START_OF_KERNEL_MEMORY) &&
(((uint32_t)BSP_DEFAULT_START_OF_KERNEL_MEMORY) < ((uint32_t)__INTERNAL_SRAM_BASE + (uint32_t)__INTERNAL_SRAM_SIZE)))
{
_BSP_sram_pool = _mem_get_system_pool_id();
}
else
{
_BSP_sram_pool = _mem_create_pool(__SRAM_POOL, (uint32_t)__INTERNAL_SRAM_BASE + (uint32_t)__INTERNAL_SRAM_SIZE - (uint32_t)__SRAM_POOL);
}
#endif
_GET_KERNEL_DATA(kernel_data);
// Initialize the slice timer to interrupt the specified
// number of times per second
kernel_data->TIMER_HW_REFERENCE = _pit_init_freq(BSP_TIMER, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK/2, FALSE);
_time_set_hwtick_function(_pit_get_hwticks, (void *)BSP_TIMER);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_pit_unmask_int(BSP_TIMER);
// Initialize and enable the serial UART interrupts
_mcf5441_int_init(BSP_UART0_INT_VECTOR, BSP_UART0_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART2_INT_VECTOR, BSP_UART2_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART4_INT_VECTOR, BSP_UART4_INT_LEVEL, TRUE);
_mcf5441_int_init(BSP_UART6_INT_VECTOR, BSP_UART6_INT_LEVEL, TRUE);
// Install and mask the DMA interrupt handler
/*
_int_install_isr(BSP_ENET_DMA_INTERRUPT, _mcf5445_dma_isr, (void *)0);
_mcf5445_int_init(BSP_ENET_DMA_INTERRUPT, BSP_ENET_DMA_INT_LEVEL, BSP_ENET_DMA_INT_PRIORITY, FALSE);
*/
// Initialize and disable the security engine interrupt
// _mcf54xx_int_init(MCF548x_INT_SEC, BSP_SEC_INT_LEVEL, /*BSP_SEC_INT_PRIORITY, */FALSE);
#if BSP_TRAP_EXCEPTIONS
_int_install_unexpected_isr();
#endif
// Always invalidate the caches even if not enabled. This allows
// us to flush the cache always. If we flush before invalidating
// very bad things happen.
_ICACHE_INVALIDATE();
_DCACHE_INVALIDATE();
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
static const PSP_MMU_INIT_STRUCT mmu_init = {
/* We define the default cacheability of non-ACR mapped regions */
/* as non-cacheable and unbuffered */
MCF54XX_CACR_DDCM(MCF54XX_CACHE_NONCACHEABLE_UNBUFFERED)
};
/* Initialize Cache Control Register CACR */
_mmu_init((void *)&mmu_init);
/* Set up 1 instruction and 1 data ACR in two separate SDRAM areas */
/* Caution: Consider memory map in linker command file before changing regions */
/* Note: Second arg to _mmu_add_region is used in mask value in ACR */
result = _mmu_add_region(__CACHED_CODE_START, __CACHED_CODE_END - __CACHED_CODE_START, PSP_MMU_EXEC_ALLOWED);
if (result != MQX_OK) return result;
result = _mmu_add_region(__CACHED_DATA_START, __CACHED_DATA_END - __CACHED_DATA_START, PSP_MMU_WRITE_THROUGH);
if (result != MQX_OK) return result;
/* Copy ACR table into ACR registers */
_MMU_ENABLE();
/* Enable instruction cache and branch history cache in CACR */
_ICACHE_ENABLE(MCF54XX_CACR_IEC | MCF54XX_CACR_BEC);
/* Enable data cache bit in CACR */
_DCACHE_ENABLE(0);
} /* Endif */
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
return 0;
}
uint_32 _bsp_enable_card
(
void
)
{
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
_GET_KERNEL_DATA(kernel_data);
_mqx_set_cpu_type(MQX_CPU);
#if MQX_EXIT_ENABLED
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
#endif
/* Memory splitter - prevent accessing both ram banks in one instruction */
_mem_alloc_at(0, (void*)0x20000000);
/* === Debugging is not allowed from here === */
/* Initialize the interrupt handling */
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
/* === Debugging may now resume === */
if (result != MQX_OK) {
return result;
}
/* set possible new interrupt vector table - if MQX_ROM_VECTORS = 0 switch to
ram interrupt table which was initialized in _psp_int_init) */
(void)_int_set_vector_table(BSP_INTERRUPT_VECTOR_TABLE);
/* Store timer interrupt vector for debugger */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
/* Install Timer ISR. */
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR, (void (_CODE_PTR_)(pointer))_bsp_systick, NULL) == NULL)
{
return MQX_TIMER_ISR_INSTALL_FAIL;
}
/** bsp low level internal initialization. ***/
_bsp_low_level_init();
/* System timer initialization */
systick_init();
/* MCG initialization and internal oscillators trimming */
if (CM_ERR_OK != _bsp_set_clock_configuration(BSP_CLOCK_CONFIGURATION_AUTOTRIM))
{
return MQX_TIMER_ISR_INSTALL_FAIL;
}
if (CM_ERR_OK != _bsp_osc_autotrim())
{
return MQX_TIMER_ISR_INSTALL_FAIL;
}
/* Switch to startup clock configuration */
if (CM_ERR_OK != _bsp_set_clock_configuration(BSP_CLOCK_CONFIGURATION_STARTUP))
{
return MQX_TIMER_ISR_INSTALL_FAIL;
}
/* Initialize the system ticks */
_GET_KERNEL_DATA(kernel_data);
kernel_data->TIMER_HW_REFERENCE = (BSP_SYSTEM_CLOCK / BSP_ALARM_FREQUENCY);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_hwtick_function(_bsp_get_hwticks, (pointer)NULL);
#if MQX_ENABLE_USER_MODE
_kinetis_mpu_init();
// supervisor full access, user no access for whole memory
_kinetis_mpu_add_region(0, ((uchar_ptr)kernel_data->INIT.START_OF_USER_NO_MEMORY) - 1, \
MPU_WORD_M3SM(MPU_SM_RWX) | MPU_WORD_M3UM(MPU_UM_R | MPU_UM_X) | \
MPU_WORD_M2SM(MPU_SM_RWX) | MPU_WORD_M2UM(MPU_UM_R | MPU_UM_X) | \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R | MPU_UM_X) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R | MPU_UM_X));
_kinetis_mpu_add_region(((uchar_ptr)kernel_data->INIT.END_OF_USER_NO_MEMORY), (uchar_ptr)0xffffffff, \
MPU_WORD_M3SM(MPU_SM_RWX) | MPU_WORD_M3UM(MPU_UM_R | MPU_UM_X) | \
MPU_WORD_M2SM(MPU_SM_RWX) | MPU_WORD_M2UM(MPU_UM_R | MPU_UM_X) | \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R | MPU_UM_X) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R | MPU_UM_X));
// set access for user memory area
#if MQX_DEFAULT_USER_ACCESS_RW
// user .data RW
_kinetis_mpu_add_region(kernel_data->INIT.START_OF_USER_DEFAULT_MEMORY, ((uchar_ptr)kernel_data->INIT.END_OF_USER_DEFAULT_MEMORY) - 1, \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R | MPU_UM_W) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R | MPU_UM_W));
#else
// user RO - this is by default
// user .data RO
/*_kinetis_mpu_add_region(kernel_data->INIT.START_OF_KERNEL_AREA, kernel_data->INIT.END_OF_KERNEL_AREA, \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R));
*/
#endif // MQX_DEFAULT_USER_ACCESS_RW
// set access for user memory area
if (0 == kernel_data->INIT.END_OF_USER_HEAP) {
// create user heap automaticaly, we have specified only size of heap (end of heap is zero, start of heap mean size)
LWMEM_POOL_STRUCT_PTR lwmem_pool_ptr;
uchar_ptr start;
//start = _lwmem_alloc((char*)kernel_data->INIT.END_OF_USER_HEAP - (char*)kernel_data->INIT.START_OF_USER_HEAP + sizeof(LWMEM_POOL_STRUCT));
start = _lwmem_alloc((uint_32)kernel_data->INIT.START_OF_USER_HEAP + sizeof(LWMEM_POOL_STRUCT));
lwmem_pool_ptr = (LWMEM_POOL_STRUCT_PTR)start;
start = (pointer)((uchar_ptr)start + sizeof(LWMEM_POOL_STRUCT));
_lwmem_create_pool(lwmem_pool_ptr, start, (uint_32)kernel_data->INIT.START_OF_USER_HEAP);
_mem_set_pool_access(lwmem_pool_ptr, POOL_USER_RW_ACCESS);
kernel_data->KD_USER_POOL = lwmem_pool_ptr;
}
else {
// manual user heap definition
_kinetis_mpu_add_region(kernel_data->INIT.START_OF_USER_HEAP, ((uchar_ptr)kernel_data->INIT.END_OF_USER_HEAP) - 1, \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R | MPU_UM_W) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R | MPU_UM_W));
}
// set access for user read-write memory area
if (kernel_data->INIT.START_OF_USER_RW_MEMORY < kernel_data->INIT.END_OF_USER_RW_MEMORY) {
_kinetis_mpu_add_region(kernel_data->INIT.START_OF_USER_RW_MEMORY, ((uchar_ptr)kernel_data->INIT.END_OF_USER_RW_MEMORY) - 1, \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R | MPU_UM_W) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R | MPU_UM_W));
}
// set access for user read-only memory area
if (kernel_data->INIT.START_OF_USER_RO_MEMORY < kernel_data->INIT.END_OF_USER_RO_MEMORY) {
_kinetis_mpu_add_region(kernel_data->INIT.START_OF_USER_RO_MEMORY, ((uchar_ptr)kernel_data->INIT.END_OF_USER_RO_MEMORY) - 1, \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(MPU_UM_R) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(MPU_UM_R));
}
// set access for user no access memory area
if (kernel_data->INIT.START_OF_USER_NO_MEMORY < kernel_data->INIT.END_OF_USER_NO_MEMORY) {
_kinetis_mpu_add_region(kernel_data->INIT.START_OF_USER_NO_MEMORY, ((uchar_ptr)kernel_data->INIT.END_OF_USER_NO_MEMORY) - 1, \
MPU_WORD_M1SM(MPU_SM_RWX) | MPU_WORD_M1UM(0) | \
MPU_WORD_M0SM(MPU_SM_RWX) | MPU_WORD_M0UM(0));
}
_kinetis_mpu_enable();
#else
_kinetis_mpu_disable();
#endif /* MQX_ENABLE_USER_MODE */
/* Install low power support */
#if MQX_ENABLE_LOW_POWER
MC_PMPROT = MC_PMPROT_AVLP_MASK | MC_PMPROT_ALLS_MASK; // allow VLPx, LLS, disallow VLLSx
_lpm_install (LPM_CPU_OPERATION_MODES, LPM_OPERATION_MODE_RUN);
#endif /* MQX_ENABLE_LOW_POWER */
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/*------------------------------------------------------------------------*/
/*
** Initialize the I/O Sub-system
*/
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize RTC and MQX time */
#if BSPCFG_ENABLE_RTCDEV
if (MQX_OK == _bsp_rtc_io_init()) {
_rtc_init (RTC_INIT_FLAG_ENABLE);
_rtc_sync_with_mqx (TRUE);
}
#endif
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
_kuart_polled_install("ttya:", &_bsp_sci0_init, _bsp_sci0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYA
_kuart_int_install("ittya:", &_bsp_sci0_init, _bsp_sci0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYB
_kuart_polled_install("ttyb:", &_bsp_sci1_init, _bsp_sci1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYB
_kuart_int_install("ittyb:", &_bsp_sci1_init, _bsp_sci1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYC
_kuart_polled_install("ttyc:", &_bsp_sci2_init, _bsp_sci2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYC
_kuart_int_install("ittyc:", &_bsp_sci2_init, _bsp_sci2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYD
_kuart_polled_install("ttyd:", &_bsp_sci3_init, _bsp_sci3_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYD
_kuart_int_install("ittyd:", &_bsp_sci3_init, _bsp_sci3_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYE
_kuart_polled_install("ttye:", &_bsp_sci4_init, _bsp_sci4_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYE
_kuart_int_install("ittye:", &_bsp_sci4_init, _bsp_sci4_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYF
_kuart_polled_install("ttyf:", &_bsp_sci5_init, _bsp_sci5_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYF
_kuart_int_install("ittyf:", &_bsp_sci5_init, _bsp_sci5_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_I2C0
_ki2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_I2C1
_ki2c_polled_install("i2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_II2C0
_ki2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C1
_ki2c_int_install("ii2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_SPI0
_dspi_polled_install("spi0:", &_bsp_dspi0_init);
#endif
#if BSPCFG_ENABLE_ISPI0
_dspi_dma_install("ispi0:", &_bsp_dspi0_init);
#endif
#if BSPCFG_ENABLE_SPI1
_dspi_polled_install("spi1:", &_bsp_dspi1_init);
#endif
#if BSPCFG_ENABLE_ISPI1
_dspi_dma_install("ispi1:", &_bsp_dspi1_init);
#endif
#if BSPCFG_ENABLE_SPI2
_dspi_polled_install("spi2:", &_bsp_dspi2_init);
#endif
#if BSPCFG_ENABLE_ISPI2
_dspi_dma_install("ispi2:", &_bsp_dspi2_init);
#endif
/* Install the GPIO driver */
#if BSPCFG_ENABLE_GPIODEV
_io_gpio_install("gpio:");
#endif
#if BSPCFG_ENABLE_ADC0
_io_adc_install("adc0:", (pointer) &_bsp_adc0_init);
#endif
#if BSPCFG_ENABLE_ADC1
_io_adc_install("adc1:", (pointer) &_bsp_adc1_init);
#endif
#if BSPCFG_ENABLE_ESDHC
_esdhc_install ("esdhc:", &_bsp_esdhc0_init);
#endif
/* Install the PCCard Flash drivers */
#if BSPCFG_ENABLE_PCFLASH
_io_pccardflexbus_install("pccarda:", (PCCARDFLEXBUS_INIT_STRUCT _PTR_) &_bsp_cfcard_init);
_io_apcflash_install("pcflasha:");
#endif
#if BSPCFG_ENABLE_FLASHX
_io_flashx_install("flashx:", &_bsp_flashx_init);
#endif
#if BSPCFG_ENABLE_IODEBUG
_io_debug_install("iodebug:", &_bsp_iodebug_init);
#endif
#if BSPCFG_ENABLE_II2S0
_ki2s_int_install("ii2s0:", &_bsp_i2s0_init);
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif // BSPCFG_ENABLE_IO_SUBSYSTEM
return MQX_OK;
}
/*!
* \brief Initializes MQXLite on the processor.
*
* The function does the following:
* \n - Initializes kernel data.
* \n - Creates the interrupt stack.
* \n - Creates the ready queues.
* \n - Creates a lightweight semaphore for task creation/destruction.
* \n - Initializes interrupts.
* \n - Initializes system timer.
*
* \param[in] mqx_init Pointer to the MQXLITE initialization structure for the
* processor.
*
* \return MQX_OK
* \return Initialization error code
*
* \warning Must be called exactly once per processor.
*
* \see _mqxlite
* \see _mqx_exit
* \see MQXLITE_INITIALIZATION_STRUCT
*/
_mqx_uint _mqxlite_init
(
MQXLITE_INITIALIZATION_STRUCT const * mqx_init
)
{ /* Body */
KERNEL_DATA_STRUCT_PTR kernel_data;
pointer stack_ptr;
_mqx_uint result = MQX_OK;
/*
* The kernel data structure starts at the start of kernel memory,
* as specified in the initialization structure. Make sure address
* specified is aligned
*/
kernel_data = (KERNEL_DATA_STRUCT_PTR) (mqx_init->START_OF_KERNEL_MEMORY);
/* Set the global pointer to the kernel data structure */
_SET_KERNEL_DATA(kernel_data);
/* The following assignments are done to force the linker to include
* the symbols, which are required by TAD.
* Note that we should use address of the variable so it is not optimized
* as direct constant assignment when optimization level is high.
* Note that counter will be immediately reset to zero on the subsequent
* _mem_zero call. */
{
MQX_INITIALIZATION_STRUCT * MQX_init_struct_ptr;
*(volatile pointer*) kernel_data = (pointer) & _mqx_version_number;
*(volatile pointer*) kernel_data = (pointer) & _mqx_vendor;
*(volatile pointer*) kernel_data = (pointer) & _mqx_path;
*(volatile pointer*) kernel_data = (pointer) & _mqxlite_version_number;
*(volatile pointer*) kernel_data = (pointer) & MQX_init_struct_ptr;
}
/* Initialize the kernel data to zero. */
_mem_zero((pointer) kernel_data, (_mem_size) sizeof(KERNEL_DATA_STRUCT));
#if MQX_CHECK_ERRORS && MQX_VERIFY_KERNEL_DATA
/* Verify that kernel data can be read and written correctly without
* errors. This is necessary during BSP development to validate the
* DRAM controller is initialized properly.
*/
if (PSP_KERNEL_DATA_VERIFY_ENABLE) {
/* This memory check is dangerous, because can destroy boot stack
* stack which is used !!! -> MQX will failed !
* Set PSP_KERNEL_DATA_VERIFY_ENABLE to 1
* only if your boot stack is out of MQX memory heap
*/
result = _mem_verify((uchar_ptr)kernel_data + sizeof(KERNEL_DATA_STRUCT),
mqx_init->END_OF_KERNEL_MEMORY);
if ( result != MQX_OK ) {
return (result); /* RETURN TO USER */
}
}
#endif /* MQX_CHECK_ERRORS && MQX_VERIFY_KERNEL_DATA */
/* Copy the MQX initialization structure into kernel data. */
kernel_data->INIT = *mqx_init;
/* init kernel data structures */
_mqx_init_kernel_data_internal();
#if MQX_USE_LWMEM == 1
/**
* Initialize lightweight memory pool for dynamic memory allocation
*/
{
/* Extern symbols defined in linker command file */
extern char __heap_addr[];
extern char __heap_size[];
KERNEL_DATA_STRUCT * kernel_data;
LWMEM_POOL_STRUCT * pool_ptr;
void * start_addr;
_GET_KERNEL_DATA(kernel_data);
pool_ptr = (LWMEM_POOL_STRUCT *) __heap_addr;
kernel_data->KERNEL_LWMEM_POOL = pool_ptr;
start_addr = (void *)((char *) __heap_addr + sizeof(LWMEM_POOL_STRUCT));
_lwmem_create_pool(pool_ptr, start_addr, (_mem_size)__heap_size);
}
#endif
#if MQX_USE_INTERRUPTS
/* Now obtain the interrupt stack */
if (kernel_data->INIT.INTERRUPT_STACK_LOCATION) {
stack_ptr = kernel_data->INIT.INTERRUPT_STACK_LOCATION;
result = kernel_data->INIT.INTERRUPT_STACK_SIZE;
}
else
{
return (MQX_INVALID_PARAMETER);
} /* Endif */
#if MQX_MONITOR_STACK
_task_fill_stack_internal((_mqx_uint_ptr)stack_ptr, result);
#endif
kernel_data->INTERRUPT_STACK_PTR = _GET_STACK_BASE(stack_ptr, result);
#endif /* MQX_USE_INTERRUPTS */
#if MQX_USE_IDLE_TASK == 0
{
/*
* Set the stack for the system TD, in case the idle task gets blocked
* by an exception or if idle task is not used.
*/
TD_STRUCT_PTR td_ptr;
uchar_ptr stack_base_ptr;
stack_base_ptr = (uchar_ptr) _GET_STACK_BASE(mqx_system_stack, PSP_MINSTACKSIZE);
td_ptr = SYSTEM_TD_PTR(kernel_data);
td_ptr->STACK_PTR = (pointer)(stack_base_ptr - sizeof(PSP_STACK_START_STRUCT));
td_ptr->STACK_BASE = stack_base_ptr;
#if MQX_TD_HAS_STACK_LIMIT
td_ptr->STACK_LIMIT = _GET_STACK_LIMIT(mqx_system_stack, PSP_MINSTACKSIZE);
#endif
_mqx_system_stack = td_ptr->STACK_PTR;
}
#endif /* MQX_USE_IDLE_TASK */
/* Build the MQX ready to run queues */
result = _psp_init_readyqs();
#if MQX_CHECK_MEMORY_ALLOCATION_ERRORS
if ( result != MQX_OK ) {
return (result); /* RETURN TO USER */
} /* Endif */
#endif
#if MQX_USE_COMPONENTS
/* Create a light wait semaphore for component creation */
_lwsem_create((LWSEM_STRUCT_PTR)&kernel_data->COMPONENT_CREATE_LWSEM, 1);
#endif
/* Create a light wait semaphore for task creation/destruction creation */
_lwsem_create((LWSEM_STRUCT_PTR) & kernel_data->TASK_CREATE_LWSEM, 1);
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
result = _psp_int_init(FIRST_INTERRUPT_VECTOR_USED, LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return(result); /* RETURN TO USER */
}
/* set possible new interrupt vector table
* if MQX_ROM_VECTORS = 0 switch to ram interrupt table which
* was initialized in _psp_int_init)
*/
_int_set_vector_table((uint32_t)(&__vect_table));
/*
* Initialize System Timer and Ticks parameters in kernel_data structure
*/
system_timer_init(NULL);
return MQX_OK; /* To satisfy lint */
} /* Endbody */
uint_32 _bsp_enable_card
(
void
)
{
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
/* Enable Timer */
_e200_enable_timer(BSP_TIMEBASE_USES_EXTERNAL_CLK);
if (_psp_core_num()==0) {
P1_Start( __boot);
}
_GET_KERNEL_DATA(kernel_data);
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MPXSxx support functions */
_mpxsxx_initialize_support();
/* Initialize the interrupt handling */
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
}
/* Initialize peripheral bridge */
//_qpbridge_init(pbridge_mprot_config, ELEMENTS_OF(pbridge_mprot_config));
/* Initialize Enhanced Interrupt Controller */
result = _qintc_install(_bsp_get_qintc_base_address(), PSP_EXCPT_EXTERNAL);
if (result != MQX_OK) {
return result;
}
/* enable processor recognition of External/Decrementer/Fit interrupts */
_PSP_SET_SR (_PSP_GET_SR() | PSP_MSR_EE);
#if BSPCFG_ENABLE_PIT_TIMER
_qpit_timer_install_kernel(BSPCFG_TIMER_PIT_DEVICE, BSPCFG_TIMER_PIT_CHANNEL,BSP_ALARM_FREQUENCY, BSP_PERI1_CLOCK, BSPCFG_TIMER_INT_LEVEL);
//_e200_decrementer_null_install();
#else
_e200_decrementer_timer_install(BSP_ALARM_FREQUENCY, BSP_TIMEBASE_CLOCK);
#endif
/*------------------------------------------------------------------------*/
/*
** Setup MMU page tables
*/
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
_mmu_init(NULL);
// First, mark the three TLBs that the boot code used as 'not-free'
_mmu_reserve_tlb(BSP_FLASH_TLB);
_mmu_reserve_tlb(BSP_RAM_TLB);
_mmu_reserve_tlb(BSP_PERIPHERAL_TLB);
// Next, add regions for RAM.
// Physical Address Virtual Address Size Attributes
_mmu_add_virtual_region(_bsp_vtop(BSP_PRIVATE_RAM_START), BSP_PRIVATE_RAM_START, BSP_PRIVATE_RAM_SIZE, BSP_PRIVATE_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtop(BSP_SHARED_RAM_START), BSP_SHARED_RAM_START, BSP_SHARED_RAM_SIZE, BSP_SHARED_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtopr(BSP_PRIVATE_RAM_START), BSP_REMOTE_PRIVATE_RAM_START,BSP_PRIVATE_RAM_SIZE, BSP_REMOTE_PRIVATE_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtopr(BSP_SHARED_RAM_START), BSP_REMOTE_SHARED_RAM_START, BSP_SHARED_RAM_SIZE, BSP_SHARED_RAM_ATTR, BSP_PID_MQX);
_mmu_add_virtual_region(_bsp_vtop(BSP_UNCACHED_DATA_START),BSP_UNCACHED_DATA_START, BSP_UNCACHED_DATA_SIZE, BSP_UNCACHED_DATA_ATTR, BSP_PID_MQX);
// switch PID from 1 (boot) to 2 (MQX)
_psp_set_pid(BSP_PID_MQX);
// Reclaim the BOOT RAM TLB
_mmu_release_tlb(BSP_RAM_TLB);
#ifndef BSP_CACHE_INHIBIT
_icache_enable(0);
_dcache_enable(0);
#endif
}
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
#if defined(__DCC__) || defined(__HIGHC__)
__init();
#elif defined(__CODEWARRIOR__)
__cpp_init();
#endif
#endif
#if BSPCFG_CORE_MUTEX
result = _core_mutex_install(&_core_mutex_init_info);
if (result != MQX_OK) {
return result;
}
#endif
/*------------------------------------------------------------------------*/
/*
** Initialize the I/O Sub-system
*/
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/* Initialize the I/O Sub-system */
result = _io_init();
if (result != MQX_OK) {
return result;
}
#if PSP_HAS_DEVICE_PROTECTION
if (!_bsp_lwgpio_enable_access(0)) {
return MQX_INVALID_DEVICE;
}
#endif
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_0)) {
_linflexd_serial_polled_install("ttya:", &_bsp_linflexd0_init);
}
#endif
#if BSPCFG_ENABLE_ITTYA
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_0)) {
_linflexd_serial_int_install("ittya:", &_bsp_linflexd0_init);
}
#endif
#if BSPCFG_ENABLE_TTYB
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_1)) {
_linflexd_serial_polled_install("ttyb:", &_bsp_linflexd1_init);
}
#endif
#if BSPCFG_ENABLE_ITTYB
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_1)) {
_linflexd_serial_int_install("ittyb:", &_bsp_linflexd1_init);
}
#endif
#if BSPCFG_ENABLE_TTYC
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_2)) {
_linflexd_serial_polled_install("ttyc:", &_bsp_linflexd2_init);
}
#endif
#if BSPCFG_ENABLE_ITTYC
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_2)) {
_linflexd_serial_int_install("ittyc:", &_bsp_linflexd2_init);
}
#endif
#if BSPCFG_ENABLE_TTYD
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_3)) {
_linflexd_serial_polled_install("ttyd:", &_bsp_linflexd3_init);
}
#endif
#if BSPCFG_ENABLE_ITTYD
if (_psp_core_peripheral_enabled(CORECFG_LINFLEX_3)) {
_linflexd_serial_int_install("ittyd:", &_bsp_linflexd3_init);
}
#endif
#if BSPCFG_ENABLE_SPI0
if (_psp_core_peripheral_enabled(CORECFG_SPI_0)) {
_io_spi_install("spi0:", &_bsp_spi0_init);
}
#endif
#if BSPCFG_ENABLE_SPI1
if (_psp_core_peripheral_enabled(CORECFG_SPI_1)) {
_io_spi_install("spi1:", &_bsp_spi1_init);
}
#endif
#if BSPCFG_ENABLE_SPI2
if (_psp_core_peripheral_enabled(CORECFG_SPI_2)) {
_io_spi_install("spi2:", &_bsp_spi2_init);
}
#endif
#if BSPCFG_ENABLE_I2C0
if (_psp_core_peripheral_enabled(CORECFG_I2C_0)) {
_qi2c_polled_install("i2c0:", &_bsp_i2c0_init);
}
#endif
#if BSPCFG_ENABLE_II2C0
if (_psp_core_peripheral_enabled(CORECFG_I2C_0)) {
_qi2c_int_install("ii2c0:", &_bsp_i2c0_init);
}
#endif
#if BSPCFG_ENABLE_I2C1
if (_psp_core_peripheral_enabled(CORECFG_I2C_1)) {
_qi2c_polled_install("i2c1:", &_bsp_i2c1_init);
}
#endif
#if BSPCFG_ENABLE_II2C1
if (_psp_core_peripheral_enabled(CORECFG_I2C_1)) {
_qi2c_int_install("ii2c1:", &_bsp_i2c1_init);
}
#endif
#if BSPCFG_ENABLE_I2C2
if (_psp_core_peripheral_enabled(CORECFG_I2C_2)) {
_qi2c_polled_install("i2c2:", &_bsp_i2c2_init);
}
#endif
#if BSPCFG_ENABLE_II2C2
if (_psp_core_peripheral_enabled(CORECFG_I2C_2)) {
_qi2c_int_install("ii2c2:", &_bsp_i2c2_init);
}
#endif
#if BSPCFG_ENABLE_FLASHX
_io_flashx_install("flashx:", &_bsp_data_flashx_init);
/* code flash support in alpha stage, not tested! */
/* _io_flashx_install("flashx_code:", &_bsp_code_flashx_init); */
#endif
#if BSPCFG_ENABLE_LWADC
#if BSPCFG_ENABLE_LWADC0
if (_psp_core_peripheral_enabled(CORECFG_ADC_0)) {
_lwadc_init(&lwadc0_init);
}
#endif
#if BSPCFG_ENABLE_LWADC1
if (_psp_core_peripheral_enabled(CORECFG_ADC_1)) {
_lwadc_init(&lwadc1_init);
}
#endif
#if BSPCFG_ENABLE_LWADC2
if (_psp_core_peripheral_enabled(CORECFG_ADC_2)) {
_lwadc_init(&lwadc2_init);
}
#endif
#if BSPCFG_ENABLE_LWADC3
if (_psp_core_peripheral_enabled(CORECFG_ADC_3)) {
_lwadc_init(&lwadc3_init);
}
#endif
#endif
#ifdef BSP_DEFAULT_IO_CHANNEL_DEFINED
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif
#endif
return MQX_OK;
}
uint_32 _bsp_enable_card
(
void
)
{ /* Body */
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
_mqx_int i;
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MCF5301x support functions */
_mcf5301_initialize_support(0);
/*
** Initialize the interrupt handling
*/
_int_set_vector_table(BSP_RAM_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED,
BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR, (void (_CODE_PTR_)(pointer))_bsp_timer_isr, NULL) == NULL) {
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
_GET_KERNEL_DATA(kernel_data);
/*
** Initialize the slice timer to interrupt the specified
** number of times per second
*/
kernel_data->TIMER_HW_REFERENCE = _mcf5301_timer_init_freq(BSP_TIMER, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK, FALSE);
_time_set_hwtick_function(_bsp_get_hwticks, 0);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
/* Initialize and enable the timer interrupt */
_mcf5301_int_init(BSP_TIMER_INTERRUPT_VECTOR, BSP_TIMER_INTERRUPT_LEVEL, /*BSP_SLICE_TIMER0_INT_PRIORITY, */TRUE);
/* Initialize and enable the serial UART interrupts */
_mcf5301_int_init(BSP_UART0_INT_VECTOR, BSP_UART0_INT_LEVEL, /*BSP_UART0_INT_PRIORITY, */TRUE);
_mcf5301_int_init(BSP_UART1_INT_VECTOR, BSP_UART1_INT_LEVEL, /*BSP_UART1_INT_PRIORITY, */TRUE);
/* Install and mask the DMA interrupt handler */
/*_int_install_isr(BSP_ENET_DMA_INTERRUPT, _mcf5301_dma_isr, (pointer)0);
_mcf5301_int_init(BSP_ENET_DMA_INTERRUPT, BSP_ENET_DMA_INT_LEVEL, BSP_ENET_DMA_INT_PRIORITY, FALSE);
*/
#if BSP_TRAP_EXCEPTIONS
_int_install_unexpected_isr();
#endif
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
static const PSP_MMU_INIT_STRUCT mmu_init = {
/* We define the default cacheability of non-ACR mapped regions */
/* as non-cacheable and unbuffered */
MCF53XX_CACR_DCM(MCF53XX_CACHE_NONCACHEABLE_UNBUFFERED)
};
/* Initialize Cache Control Register CACR */
_mmu_init((pointer)&mmu_init);
/* Set up 1 instruction and 1 data ACR in two separate SDRAM areas */
/* Caution: Consider memory map in linker command file before changing regions */
/* Note: Second arg to _mmu_add_region is used in mask value in ACR */
result = _mmu_add_region(__CACHED_CODE_START, __CACHED_CODE_END - __CACHED_CODE_START, PSP_MMU_EXEC_ALLOWED);
if (result != MQX_OK)
return result;
result = _mmu_add_region(__UNCACHED_DATA_START, __UNCACHED_DATA_END - __UNCACHED_DATA_START, PSP_MMU_DATA_CACHE_INHIBITED);
if (result != MQX_OK)
return result;
/* Copy ACR table into ACR registers */
_MMU_ENABLE();
/* Enable cache
** 0 - Instruction cache only
** 1 - Data cache only
** 2 - Both Instruction & Data cache
*/
_CACHE_ENABLE(2);
} /* Endif */
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
/* Initialize RTC and MQX time */
#if BSPCFG_ENABLE_RTCDEV
_bsp_rtc_io_init ();
_rtc_sync_with_mqx (TRUE);
#endif
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/* Initialize the I/O Sub-system */
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
#if BSPCFG_ENABLE_TTYA
_mcf53xx_uart_serial_polled_install("ttya:", &_bsp_uart0_init, _bsp_uart0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYB
_mcf53xx_uart_serial_polled_install("ttyb:", &_bsp_uart1_init, _bsp_uart1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYC
_mcf53xx_uart_serial_polled_install("ttyc:", &_bsp_uart2_init, _bsp_uart2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYA
_mcf53xx_uart_serial_int_install("ittya:", &_bsp_uart0_init, _bsp_uart0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYB
_mcf53xx_uart_serial_int_install("ittyb:", &_bsp_uart1_init, _bsp_uart1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYC
_mcf53xx_uart_serial_int_install("ittyc:", &_bsp_uart2_init, _bsp_uart2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_I2C0
_mcf53xx_i2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C0
_mcf53xx_i2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_SPI0
_mcf5xxx_dspi_polled_install("spi0:", &_bsp_dspi0_init);
#endif
#if BSPCFG_ENABLE_ISPI0
_mcf5xxx_dspi_int_install("ispi0:", &_bsp_dspi0_init);
#endif
#if BSPCFG_ENABLE_EXT_FLASH
result = _io_flashx_install(&_bsp_flashx_init);
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif /* BSPCFG_ENABLE_IO_SUBSYSTEM */
/*#if !BSP_PEG_PCI_ENABLE
Initialize the PCI in master mode. This will enumerate the bus.
_io_pci_init(TRUE);
#endif
*/
/* Install the GPIO driver */
#if BSPCFG_ENABLE_GPIODEV
_io_gpio_install("gpio:");
#endif
#if BSPCFG_ENABLE_ESDHC
_esdhc_install ("esdhc:", &_bsp_esdhc_init);
#endif
return MQX_OK;
} /* Endbody */
uint_32 _bsp_enable_card
(
void
)
{
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
_GET_KERNEL_DATA(kernel_data);
_mqx_set_cpu_type(PSP_CPU_MPXN20);
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
/* Initialize the MPXNxx MMU support functions */
_mpxnxx_initialize_support();
/* === Debugging is not allowed from here === */
/* Initialize the interrupt handling */
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED, BSP_LAST_INTERRUPT_VECTOR_USED);
/* === Debugging may now resume === */
if (result != MQX_OK) {
return result;
}
result = _qintc_install(_bsp_get_qintc_base_address(), PSP_EXCPT_EXTERNAL);
if (result != MQX_OK) {
return result;
}
/* enable processor recognition of External/Decrementer/Fit interrupts */
_PSP_SET_SR (_PSP_GET_SR() | PSP_MSR_EE);
#if 0
/* Install program exception handler */
if (_int_install_isr(PSP_EXCPT_PROGRAM, _psp_program_isr, NULL) == NULL)
{
return _task_get_error();
}
#endif
#if BSPCFG_ENABLE_PIT_TIMER
_qpit_timer_install_kernel(BSPCFG_TIMER_PIT_DEVICE, BSPCFG_TIMER_PIT_CHANNEL, BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK, BSPCFG_TIMER_INT_LEVEL);
#else
_e200_decrementer_timer_install(BSP_ALARM_FREQUENCY, BSP_TIMEBASE_CLOCK);
#endif
/*------------------------------------------------------------------------*/
/*
** Setup MMU page tables
*/
if (_mqx_monitor_type == MQX_MONITOR_TYPE_NONE) {
_mmu_init(NULL);
/* First, mark the three TLBs that the boot code used as 'not-free' */
_mmu_reserve_tlb(BSP_FLASH_TLB);
_mmu_reserve_tlb(BSP_INT_SRAM_TLB);
/* Periph B Modules */
_mmu_reserve_tlb(BSP_PERIPHERAL_TLB);
_mmu_reserve_tlb(BSP_EXT_RAM_TLB);
_mmu_reserve_tlb(BSP_PERIPHERAL_A_TLB);
/* Next, add regions for RAM.
** Physical Address Virtual Address Size Attributes
*/
//_mmu_add_virtual_region((BSP_PRIVATE_RAM_START), BSP_PRIVATE_RAM_START, BSP_PRIVATE_RAM_SIZE, BSP_PRIVATE_RAM_ATTR, BSP_PID_MQX);
//_mmu_add_virtual_region((BSP_UNCACHED_DATA_START),BSP_UNCACHED_DATA_START, BSP_UNCACHED_DATA_SIZE, BSP_UNCACHED_DATA_ATTR, BSP_PID_MQX);
/* switch PID from 1 (boot) to 2 (MQX) */
/*_psp_set_pid(BSP_PID_MQX);*/
/*Reclaim the BOOT RAM TLB*/
/*_mmu_release_tlb(BSP_RAM_TLB);*/
#ifndef BSP_CACHE_INHIBIT
_icache_enable(0);
_dcache_enable(0);
#endif
}
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
#if defined(__DCC__) || defined(__HIGHC__)
__init();
#elif defined(__CODEWARRIOR__)
__cpp_init();
#endif
#endif //BSPCFG_ENABLE_CPP
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/*------------------------------------------------------------------------*/
/*
** Initialize the I/O Sub-system
*/
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
_lin_serial_polled_install("ttya:", &_bsp_lin0_init);
#endif
#if BSPCFG_ENABLE_ITTYA
_lin_serial_int_install("ittya:", &_bsp_lin0_init);
#endif
#if BSPCFG_ENABLE_TTYB
_lin_serial_polled_install("ttyb:", &_bsp_lin1_init);
#endif
#if BSPCFG_ENABLE_ITTYB
_lin_serial_int_install("ittyb:", &_bsp_lin1_init);
#endif
#if BSPCFG_ENABLE_TTYC
_lin_serial_polled_install("ttyc:", &_bsp_lin2_init);
#endif
#if BSPCFG_ENABLE_ITTYC
_lin_serial_int_install("ittyc:", &_bsp_lin2_init);
#endif
#if BSPCFG_ENABLE_TTYD
_lin_serial_polled_install("ttyd:", &_bsp_lin3_init);
#endif
#if BSPCFG_ENABLE_ITTYD
_lin_serial_int_install("ittyd:", &_bsp_lin3_init);
#endif
#if BSPCFG_ENABLE_TTYE
_lin_serial_polled_install("ttye:", &_bsp_lin4_init);
#endif
#if BSPCFG_ENABLE_ITTYE
_lin_serial_int_install("ittye:", &_bsp_lin4_init);
#endif
#if BSPCFG_ENABLE_TTYF
_lin_serial_polled_install("ttyf:", &_bsp_lin5_init);
#endif
#if BSPCFG_ENABLE_ITTYF
_lin_serial_int_install("ittyf:", &_bsp_lin5_init);
#endif
#if BSPCFG_ENABLE_SPI0
_io_spi_install("spi0:", &_bsp_spi0_init);
#endif
#if BSPCFG_ENABLE_SPI1
_io_spi_install("spi1:", &_bsp_spi1_init);
#endif
#if BSPCFG_ENABLE_SPI2
_io_spi_install("spi2:", &_bsp_spi2_init);
#endif
#if BSPCFG_ENABLE_SPI3
_io_spi_install("spi3:", &_bsp_spi3_init);
#endif
#if BSPCFG_ENABLE_FLASHX
_io_flashx_install("flashx:", &_bsp_flashx_init);
#endif
#if BSPCFG_ENABLE_I2C0
_qi2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C0
_qi2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_I2C1
_qi2c_polled_install("i2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_II2C1
_qi2c_int_install("ii2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_I2C2
_qi2c_polled_install("i2c2:", &_bsp_i2c2_init);
#endif
#if BSPCFG_ENABLE_II2C2
_qi2c_int_install("ii2c2:", &_bsp_i2c2_init);
#endif
#if BSPCFG_ENABLE_I2C3
_qi2c_polled_install("i2c3:", &_bsp_i2c3_init);
#endif
#if BSPCFG_ENABLE_II2C3
_qi2c_int_install("ii2c3:", &_bsp_i2c3_init);
#endif
#if BSPCFG_ENABLE_RTCDEV
_rtc_init (RTC_INIT_FLAG_CLEAR | RTC_INIT_FLAG_RESET | RTC_INIT_FLAG_ENABLE);
#endif
#if BSPCFG_ENABLE_LWADC
#if BSPCFG_ENABLE_LWADC0
_lwadc_init(&lwadc0_init);
#endif
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
#endif // BSPCFG_ENABLE_IO_SUBSYSTEM
return MQX_OK;
}
uint_32 _bsp_enable_card
(
void
)
{ /* Body */
KERNEL_DATA_STRUCT_PTR kernel_data;
uint_32 result;
/* Set the CPU type */
_mqx_set_cpu_type(MQX_CPU);
#if MQX_EXIT_ENABLED
/* Set the bsp exit handler, called by _mqx_exit */
_mqx_set_exit_handler(_bsp_exit_handler);
#endif
/* Initialize the MCF5225 support functions */
_mcf5225_initialize_support(0);
/*
** Initialize the interrupt handling
*/
/* Mask all interrupts */
_mcf5225_int_mask_all();
_int_set_vector_table(BSP_INTERRUPT_VECTOR_TABLE);
result = _psp_int_init(BSP_FIRST_INTERRUPT_VECTOR_USED,
BSP_LAST_INTERRUPT_VECTOR_USED);
if (result != MQX_OK) {
return result;
} /* Endif */
/* Initialize the timer interrupt */
_time_set_timer_vector(BSP_TIMER_INTERRUPT_VECTOR);
if (_int_install_isr(BSP_TIMER_INTERRUPT_VECTOR,
(void (_CODE_PTR_)(pointer))_bsp_timer_isr, NULL) == NULL)
{
return MQX_TIMER_ISR_INSTALL_FAIL;
} /* Endif */
_GET_KERNEL_DATA(kernel_data);
kernel_data->TIMER_HW_REFERENCE = _mcf5225_timer_init_freq(BSP_TIMER,
BSP_ALARM_FREQUENCY, BSP_SYSTEM_CLOCK, FALSE);
_time_set_hwtick_function(_bsp_get_hwticks,
(pointer)kernel_data->TIMER_HW_REFERENCE);
_time_set_hwticks_per_tick(kernel_data->TIMER_HW_REFERENCE);
_time_set_ticks_per_sec(BSP_ALARM_FREQUENCY);
_mcf5225_timer_unmask_int(BSP_TIMER);
#if BSPCFG_ENABLE_CPP
/* initialize C++ constructors */
__cpp_init();
#endif
/* Initialize RTC and MQX time */
#if BSPCFG_ENABLE_RTCDEV
_bsp_rtc_io_init ();
_rtc_sync_with_mqx (TRUE);
#endif
#if BSPCFG_ENABLE_IO_SUBSYSTEM
/* Initialize the I/O Sub-system */
result = _io_init();
if (result != MQX_OK) {
return result;
} /* Endif */
/* Install device drivers */
#if BSPCFG_ENABLE_TTYA
_mcf52xx_uart_serial_polled_install("ttya:", &_bsp_uart0_init,
_bsp_uart0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYB
_mcf52xx_uart_serial_polled_install("ttyb:", &_bsp_uart1_init,
_bsp_uart1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_TTYC
_mcf52xx_uart_serial_polled_install("ttyc:", &_bsp_uart2_init,
_bsp_uart2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYA
_mcf52xx_uart_serial_int_install("ittya:", &_bsp_uart0_init,
_bsp_uart0_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYB
_mcf52xx_uart_serial_int_install("ittyb:", &_bsp_uart1_init,
_bsp_uart1_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_ITTYC
_mcf52xx_uart_serial_int_install("ittyc:", &_bsp_uart2_init,
_bsp_uart2_init.QUEUE_SIZE);
#endif
#if BSPCFG_ENABLE_I2C0
_mcf52xx_i2c_polled_install("i2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_I2C1
_mcf52xx_i2c_polled_install("i2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_II2C0
_mcf52xx_i2c_int_install("ii2c0:", &_bsp_i2c0_init);
#endif
#if BSPCFG_ENABLE_II2C1
_mcf52xx_i2c_int_install("ii2c1:", &_bsp_i2c1_init);
#endif
#if BSPCFG_ENABLE_SPI0
_mcf5xxx_qspi_polled_install("spi0:", &_bsp_qspi0_init);
#endif
#if BSPCFG_ENABLE_ISPI0
_mcf5xxx_qspi_int_install("ispi0:", &_bsp_qspi0_init);
#endif
#if BSPCFG_ENABLE_ADC
_io_adc_install("adc:", NULL);
#endif
/* Initialize the default serial I/O */
_io_serial_default_init();
/* Install the GPIO driver */
#if BSPCFG_ENABLE_GPIODEV
_io_gpio_install("gpio:");
#endif
/* install internal flash */
#if BSPCFG_ENABLE_FLASHX
_mcf5225_internal_flash_install("flashx:", BSPCFG_FLASHX_SIZE);
#endif
#endif
/*
** Enable/disable the watchdog timer
** The initialization mode is defined by BSP_WATCHDOG_INITIALIZATION macro
*/
_bsp_setup_watchdog();
return MQX_OK;
} /* Endbody */
