/* Checks "l3cr=xxxx" command-line option */
int __init ppc_setup_l3cr(char *str)
{
if (cpu_has_feature(CPU_FTR_L3CR)) {
unsigned long val = simple_strtoul(str, NULL, 0);
printk(KERN_INFO "l3cr set to %lx\n", val);
_set_L3CR(val); /* and enable it */
}
return 1;
}
static void __init
sandpoint_setup_arch(void)
{
loops_per_jiffy = 100000000 / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = to_kdev_t(0x00FF); /* /dev/nfs pseudo device */
#else
ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 IDE disk */
#endif
/* Lookup PCI host bridges */
sandpoint_find_bridges();
#ifdef CONFIG_SERIAL
sandpoint_early_serial_map();
#endif
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
/* DINK32 12.3 and below do not correctly enable any caches.
* We will do this now with good known values. Future versions
* of DINK32 are supposed to get this correct.
*/
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450)
/* 745x is different. We only want to pass along enable. */
_set_L2CR(L2CR_L2E);
else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)
/* All modules have 1MB of L2. We also assume that an
* L2 divisor of 3 will work.
*/
_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
| L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
#if 0
/* Untested right now. */
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) {
/* Magic value. */
_set_L3CR(0x8f032000);
}
#endif
}
static void __init
sandpoint_setup_arch(void)
{
/* Probe for Sandpoint model */
sandpoint_probe_type();
if (sandpoint_is_x2)
epic_serial_mode = 0;
loops_per_jiffy = 100000000 / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
/* Lookup PCI host bridges */
sandpoint_find_bridges();
if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
{
bd_t *bp = (bd_t *)__res;
struct plat_serial8250_port *pdata;
pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
if (pdata)
{
pdata[0].uartclk = bp->bi_busfreq;
}
#ifdef CONFIG_SANDPOINT_ENABLE_UART1
pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
if (pdata)
{
pdata[0].uartclk = bp->bi_busfreq;
}
#else
ppc_sys_device_remove(MPC10X_UART1);
#endif
}
printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
printk(KERN_INFO "Port by MontaVista Software, Inc. ([email protected])\n");
/* DINK32 12.3 and below do not correctly enable any caches.
* We will do this now with good known values. Future versions
* of DINK32 are supposed to get this correct.
*/
if (cpu_has_feature(CPU_FTR_SPEC7450))
/* 745x is different. We only want to pass along enable. */
_set_L2CR(L2CR_L2E);
else if (cpu_has_feature(CPU_FTR_L2CR))
/* All modules have 1MB of L2. We also assume that an
* L2 divisor of 3 will work.
*/
_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
| L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
#if 0
/* Untested right now. */
if (cpu_has_feature(CPU_FTR_L3CR)) {
/* Magic value. */
_set_L3CR(0x8f032000);
}
#endif
}
