static int
audioixp_resume(dev_info_t *dip)
{
audioixp_state_t *statep;
audio_dev_t *adev;
audioixp_port_t *rec_port, *play_port;
statep = ddi_get_driver_private(dip);
adev = statep->adev;
ASSERT(statep != NULL);
if (audioixp_chip_init(statep) != DDI_SUCCESS) {
audio_dev_warn(adev, "DDI_RESUME failed to init chip");
return (DDI_SUCCESS);
}
ac97_resume(statep->ac97);
mutex_enter(&statep->inst_lock);
statep->suspended = B_FALSE;
rec_port = statep->rec_port;
play_port = statep->play_port;
audioixp_resume_port(rec_port);
audioixp_resume_port(play_port);
mutex_exit(&statep->inst_lock);
return (DDI_SUCCESS);
}
void
eap_resume(struct eap_softc *sc)
{
int i;
if (!sc->sc_1371) {
/* Enable interrupts and looping mode. */
/* enable the parts we need */
EWRITE4(sc, EAP_SIC, EAP_P2_INTR_EN | EAP_R1_INTR_EN);
EWRITE4(sc, EAP_ICSC, EAP_CDC_EN);
/* reset codec */
/* normal operation */
/* select codec clocks */
eap1370_write_codec(sc, AK_RESET, AK_PD);
eap1370_write_codec(sc, AK_RESET, AK_PD | AK_NRST);
eap1370_write_codec(sc, AK_CS, 0x0);
} else {
/* clean slate */
EWRITE4(sc, EAP_SIC, 0);
EWRITE4(sc, EAP_ICSC, 0);
EWRITE4(sc, E1371_LEGACY, 0);
if (sc->sc_ct5880) {
EWRITE4(sc, EAP_ICSS, EAP_CT5880_AC97_RESET);
/* Let codec wake up */
delay(20000);
}
ac97_resume(&sc->host_if, sc->codec_if);
EWRITE4(sc, E1371_SRC, E1371_SRC_DISABLE);
for (i = 0; i < 0x80; i++)
eap1371_src_write(sc, i, 0);
eap1371_src_write(sc, ESRC_ADC + ESRC_TRUNC_N, ESRC_SET_N(16));
eap1371_src_write(sc, ESRC_ADC + ESRC_IREGS, ESRC_SET_VFI(16));
eap1371_src_write(sc, ESRC_ADC + ESRC_VFF, 0);
eap1371_src_write(sc, ESRC_ADC_VOLL, ESRC_SET_ADC_VOL(16));
eap1371_src_write(sc, ESRC_ADC_VOLR, ESRC_SET_ADC_VOL(16));
eap1371_src_write(sc, ESRC_DAC1 + ESRC_TRUNC_N, ESRC_SET_N(16));
eap1371_src_write(sc, ESRC_DAC1 + ESRC_IREGS, ESRC_SET_VFI(16));
eap1371_src_write(sc, ESRC_DAC1 + ESRC_VFF, 0);
eap1371_src_write(sc, ESRC_DAC1_VOLL, ESRC_SET_DAC_VOLI(1));
eap1371_src_write(sc, ESRC_DAC1_VOLR, ESRC_SET_DAC_VOLI(1));
eap1371_src_write(sc, ESRC_DAC2 + ESRC_IREGS, ESRC_SET_VFI(16));
eap1371_src_write(sc, ESRC_DAC2 + ESRC_TRUNC_N, ESRC_SET_N(16));
eap1371_src_write(sc, ESRC_DAC2 + ESRC_VFF, 0);
eap1371_src_write(sc, ESRC_DAC2_VOLL, ESRC_SET_DAC_VOLI(1));
eap1371_src_write(sc, ESRC_DAC2_VOLR, ESRC_SET_DAC_VOLI(1));
EWRITE4(sc, E1371_SRC, 0);
/* Interrupt enable */
EWRITE4(sc, EAP_SIC, EAP_P2_INTR_EN | EAP_R1_INTR_EN);
}
}
int
auvia_resume(struct auvia_softc *sc)
{
pci_conf_read(sc->sc_pc, sc->sc_pt, AUVIA_PCICONF_JUNK);
pci_conf_write(sc->sc_pc, sc->sc_pt, AUVIA_PCICONF_JUNK,
sc->sc_pci_junk);
ac97_resume(&sc->host_if, sc->codec_if);
return (0);
}
int
eap_resume(struct eap_softc *sc)
{
mixer_ctrl_t ctl;
int i;
if (!sc->sc_1371) {
/* Enable interrupts and looping mode. */
/* enable the parts we need */
EWRITE4(sc, EAP_SIC, EAP_P2_INTR_EN | EAP_R1_INTR_EN);
EWRITE4(sc, EAP_ICSC, EAP_CDC_EN);
/* reset codec */
/* normal operation */
/* select codec clocks */
eap1370_write_codec(sc, AK_RESET, AK_PD);
eap1370_write_codec(sc, AK_RESET, AK_PD | AK_NRST);
eap1370_write_codec(sc, AK_CS, 0x0);
bzero(&ctl, sizeof(ctl));
ctl.dev = EAP_RECORD_SOURCE;
ctl.type = AUDIO_MIXER_SET;
ctl.un.mask = sc->sc_record_source;
eap1370_hw_if.set_port(sc, &ctl);
ctl.dev = EAP_INPUT_SOURCE;
ctl.type = AUDIO_MIXER_SET;
ctl.un.mask = sc->sc_input_source;
eap1370_hw_if.set_port(sc, &ctl);
eap1370_set_mixer(sc, AK_MGAIN, sc->sc_mic_preamp);
for (i = EAP_MASTER_VOL; i < EAP_MIC_VOL; i++)
eap1370_write_codec(sc, i, sc->sc_port[i]);
} else {
/* clean slate */
EWRITE4(sc, EAP_SIC, 0);
EWRITE4(sc, EAP_ICSC, 0);
EWRITE4(sc, E1371_LEGACY, 0);
if (sc->sc_ct5880) {
EWRITE4(sc, EAP_ICSS, EAP_CT5880_AC97_RESET);
/* Let codec wake up */
delay(20000);
}
ac97_resume(&sc->host_if, sc->codec_if);
EWRITE4(sc, E1371_SRC, E1371_SRC_DISABLE);
for (i = 0; i < 0x80; i++)
eap1371_src_write(sc, i, 0);
eap1371_src_write(sc, ESRC_ADC + ESRC_TRUNC_N, ESRC_SET_N(16));
eap1371_src_write(sc, ESRC_ADC + ESRC_IREGS, ESRC_SET_VFI(16));
eap1371_src_write(sc, ESRC_ADC + ESRC_VFF, 0);
eap1371_src_write(sc, ESRC_ADC_VOLL, ESRC_SET_ADC_VOL(16));
eap1371_src_write(sc, ESRC_ADC_VOLR, ESRC_SET_ADC_VOL(16));
eap1371_src_write(sc, ESRC_DAC1 + ESRC_TRUNC_N, ESRC_SET_N(16));
eap1371_src_write(sc, ESRC_DAC1 + ESRC_IREGS, ESRC_SET_VFI(16));
eap1371_src_write(sc, ESRC_DAC1 + ESRC_VFF, 0);
eap1371_src_write(sc, ESRC_DAC1_VOLL, ESRC_SET_DAC_VOLI(1));
eap1371_src_write(sc, ESRC_DAC1_VOLR, ESRC_SET_DAC_VOLI(1));
eap1371_src_write(sc, ESRC_DAC2 + ESRC_IREGS, ESRC_SET_VFI(16));
eap1371_src_write(sc, ESRC_DAC2 + ESRC_TRUNC_N, ESRC_SET_N(16));
eap1371_src_write(sc, ESRC_DAC2 + ESRC_VFF, 0);
eap1371_src_write(sc, ESRC_DAC2_VOLL, ESRC_SET_DAC_VOLI(1));
eap1371_src_write(sc, ESRC_DAC2_VOLR, ESRC_SET_DAC_VOLI(1));
EWRITE4(sc, E1371_SRC, 0);
/* Interrupt enable */
EWRITE4(sc, EAP_SIC, EAP_P2_INTR_EN | EAP_R1_INTR_EN);
}
return (0);
}
