/***************************************************************************//**
* @brief Starts the sweep operation.
*
* @param dev - The device structure.
*
* @return None.
*******************************************************************************/
void ad5933_start_sweep(struct ad5933_dev *dev)
{
uint8_t status = 0;
ad5933_set_register_value(dev,
AD5933_REG_CONTROL_HB,
AD5933_CONTROL_FUNCTION(AD5933_FUNCTION_STANDBY) |
AD5933_CONTROL_RANGE(dev->current_range) |
AD5933_CONTROL_PGA_GAIN(dev->current_gain),
1);
ad5933_reset(dev);
ad5933_set_register_value(dev,
AD5933_REG_CONTROL_HB,
AD5933_CONTROL_FUNCTION(AD5933_FUNCTION_INIT_START_FREQ)|
AD5933_CONTROL_RANGE(dev->current_range) |
AD5933_CONTROL_PGA_GAIN(dev->current_gain),
1);
ad5933_set_register_value(dev,
AD5933_REG_CONTROL_HB,
AD5933_CONTROL_FUNCTION(AD5933_FUNCTION_START_SWEEP) |
AD5933_CONTROL_RANGE(dev->current_range) |
AD5933_CONTROL_PGA_GAIN(dev->current_gain),
1);
status = 0;
while((status & AD5933_STAT_DATA_VALID) == 0) {
status = ad5933_get_register_value(dev,
AD5933_REG_STATUS,
1);
};
}
int ad5933_ring_preenable()
{
AD5933_STATE *st = &g_st;
int32_t ret;
ret = ad5933_reset(st);
if (ret == ERROR)
return ret;
ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
if (ret == ERROR)
return ret;
ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
if (ret == ERROR)
return ret;
st->state = AD5933_CTRL_INIT_START_FREQ;
return 0;
}
/*
AD5934
- Reset
- Start Freguency
- Increntment Frequency
*/
static int ad5933_setup(AD5933_STATE *st)
{
union {
uint16_t d16;
uint8_t d8[2];
} dat;
int ret;
ret = ad5933_reset(st);
if (ret == ERROR)
return ret;
ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
if (ret == ERROR)
return ret;
ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
if (ret == ERROR)
return ret;
/*
NUMBER OF SETTLING TIME CYCLES REGISTER
@REGISTER ADDRESS 0x8A
@REGISTER ADDRESS 0x8B
The maximum number of output cycles that can be programmed is 511 × 4 = 2044 cycles.
For example, consider an excitation signal of 30 kHz,
the maximum delay between the programming of this frequency
and the time that this signal is first sampled by the ADC is ˜ 511 × 4 × 33.33 µs = 68.126 ms.
The ADC takes 1024 samples, and the result is stored as real data and imaginary data in Register Address 0x94
to Register Address 0x97.
The conversion process takes approximately 1 ms using a 16.777 MHz clock.
*/
st->settling_cycles = 10;
dat.d16 = cpu_to_be16(st->settling_cycles);
ret = ad5933_i2c_write(AD5933_REG_SETTLING_CYCLES, 2, dat.d8[0]);
ret = ad5933_i2c_write(AD5933_REG_SETTLING_CYCLES+1, 2, dat.d8[1]);
if (ret == ERROR)
return ret;
/*
NUMBER OF INCREMENTS REGISTER
@REGISTER ADDRESS 0x88
@REGISTER ADDRESS 0x89
This register determines the number of frequency points in the frequency sweep.
The number of frequency points is represented by a 9-bit word,
D8 to D0. D15 to D9 are don’t care bits.
This register in conjunction with the start frequency register and
the frequency increment register determine the frequency sweep range for the sweep operation.
The maximum number of increments that can be programmed is 511.
*/
st->freq_points = 100;
dat.d16 = cpu_to_be16(st->freq_points);
ret = ad5933_i2c_write(AD5933_REG_INC_NUM, 2, dat.d8[0]);
ret = ad5933_i2c_write(AD5933_REG_INC_NUM+1, 2, dat.d8[1]);
return ret;
}
