void __init kirkwood_pcie_init(unsigned int portmask)
{
if (portmask & KW_PCIE0)
add_pcie_port(0, PCIE_VIRT_BASE);
if (portmask & KW_PCIE1)
add_pcie_port(1, PCIE1_VIRT_BASE);
kirkwood_pci.nr_controllers = num_pcie_ports;
pci_common_init(&kirkwood_pci);
}
void __init dove_pcie_init(int init_port0, int init_port1)
{
vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
if (init_port0)
add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
if (init_port1)
add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
pci_common_init(&dove_pci);
}
void __init mv78xx0_pcie_init(int init_port0, int init_port1)
{
vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
if (init_port0) {
add_pcie_port(0, 0, PCIE00_VIRT_BASE);
if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
add_pcie_port(0, 1, PCIE01_VIRT_BASE);
add_pcie_port(0, 2, PCIE02_VIRT_BASE);
add_pcie_port(0, 3, PCIE03_VIRT_BASE);
}
}
if (init_port1) {
add_pcie_port(1, 0, PCIE10_VIRT_BASE);
if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
add_pcie_port(1, 1, PCIE11_VIRT_BASE);
add_pcie_port(1, 2, PCIE12_VIRT_BASE);
add_pcie_port(1, 3, PCIE13_VIRT_BASE);
}
}
pci_common_init(&mv78xx0_pci);
}
static int __init exynos_pcie_probe(struct platform_device *pdev)
{
struct exynos_pcie *exynos_pcie;
struct pcie_port *pp;
struct device_node *np = pdev->dev.of_node;
struct resource *elbi_base;
struct resource *phy_base;
struct resource *block_base;
struct resource *pmu_base;
int ret;
exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
GFP_KERNEL);
if (!exynos_pcie) {
dev_err(&pdev->dev, "no memory for exynos pcie\n");
return -ENOMEM;
}
pp = &exynos_pcie->pp;
pp->dev = &pdev->dev;
exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
if (IS_ERR(exynos_pcie->clk)) {
dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
return PTR_ERR(exynos_pcie->clk);
}
ret = clk_prepare_enable(exynos_pcie->clk);
if (ret)
return ret;
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
if (IS_ERR(exynos_pcie->elbi_base))
return PTR_ERR(exynos_pcie->elbi_base);
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
if (IS_ERR(exynos_pcie->phy_base))
return PTR_ERR(exynos_pcie->phy_base);
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
if (IS_ERR(exynos_pcie->block_base))
return PTR_ERR(exynos_pcie->block_base);
pmu_base = platform_get_resource(pdev, IORESOURCE_MEM, 3);
exynos_pcie->pmu_base = devm_ioremap_resource(&pdev->dev, pmu_base);
if (IS_ERR(exynos_pcie->pmu_base))
return PTR_ERR(exynos_pcie->pmu_base);
ret = add_pcie_port(pp, pdev);
if (ret > 0)
goto fail_bus_clk;
platform_set_drvdata(pdev, exynos_pcie);
return 0;
fail_bus_clk:
clk_disable_unprepare(exynos_pcie->bus_clk);
//fail_clk:
// clk_disable_unprepare(exynos_pcie->clk);
return ret;
}
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
u32 reg;
int ret;
int irq;
int i;
int phy_count;
struct phy **phy;
void __iomem *base;
struct resource *res;
struct dra7xx_pcie *dra7xx;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
char name[10];
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
return -ENOMEM;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "missing IRQ resource\n");
return -EINVAL;
}
ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
if (ret) {
dev_err(dev, "failed to request irq\n");
return ret;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
base = devm_ioremap_nocache(dev, res->start, resource_size(res));
if (!base)
return -ENOMEM;
phy_count = of_property_count_strings(np, "phy-names");
if (phy_count < 0) {
dev_err(dev, "unable to find the strings\n");
return phy_count;
}
phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
if (!phy)
return -ENOMEM;
for (i = 0; i < phy_count; i++) {
snprintf(name, sizeof(name), "pcie-phy%d", i);
phy[i] = devm_phy_get(dev, name);
if (IS_ERR(phy[i]))
return PTR_ERR(phy[i]);
ret = phy_init(phy[i]);
if (ret < 0)
goto err_phy;
ret = phy_power_on(phy[i]);
if (ret < 0) {
phy_exit(phy[i]);
goto err_phy;
}
}
dra7xx->base = base;
dra7xx->phy = phy;
dra7xx->dev = dev;
dra7xx->phy_count = phy_count;
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "pm_runtime_get_sync failed\n");
goto err_phy;
}
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
reg &= ~LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
platform_set_drvdata(pdev, dra7xx);
ret = add_pcie_port(dra7xx, pdev);
if (ret < 0)
goto err_add_port;
return 0;
err_add_port:
pm_runtime_put(dev);
pm_runtime_disable(dev);
err_phy:
while (--i >= 0) {
phy_power_off(phy[i]);
phy_exit(phy[i]);
}
return ret;
}