void genadd(void)
{
#ifdef INTERPRET_ADD
gencallinterp((unsigned int)cached_interpreter_table.ADD, 0);
#else
int rs = allocate_register((unsigned int *)dst->f.r.rs);
int rt = allocate_register((unsigned int *)dst->f.r.rt);
int rd = allocate_register_w((unsigned int *)dst->f.r.rd);
if (rt != rd && rs != rd)
{
mov_reg32_reg32(rd, rs);
add_reg32_reg32(rd, rt);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs);
add_reg32_reg32(temp, rt);
mov_reg32_reg32(rd, temp);
}
#endif
}
void genaddu(usf_state_t * state)
{
#ifdef INTERPRET_ADDU
gencallinterp(state, (unsigned int)state->current_instruction_table.ADDU, 0);
#else
int rs = allocate_register(state, (unsigned int *)state->dst->f.r.rs);
int rt = allocate_register(state, (unsigned int *)state->dst->f.r.rt);
int rd = allocate_register_w(state, (unsigned int *)state->dst->f.r.rd);
if (rt != rd && rs != rd)
{
mov_reg32_reg32(state, rd, rs);
add_reg32_reg32(state, rd, rt);
}
else
{
int temp = lru_register(state);
free_register(state, temp);
mov_reg32_reg32(state, temp, rs);
add_reg32_reg32(state, temp, rt);
mov_reg32_reg32(state, rd, temp);
}
#endif
}
