uint8_t debug_read_byte(uint32_t address) {
uint8_t *ptr, value = 0;
address &= 0xFFFFFF;
if (address < 0xE00000) {
if ((ptr = phys_mem_ptr(address, 1))) {
value = *ptr;
}
} else {
value = debug_port_read_byte(mmio_range(address)<<12 | addr_range(address));
}
if (debugger.data.block[address]) {
disasmHighlight.hit_read_breakpoint = debugger.data.block[address] & DBG_READ_BREAKPOINT;
disasmHighlight.hit_write_breakpoint = debugger.data.block[address] & DBG_WRITE_BREAKPOINT;
disasmHighlight.hit_exec_breakpoint = debugger.data.block[address] & DBG_EXEC_BREAKPOINT;
disasmHighlight.hit_run_breakpoint = debugger.data.block[address] & DBG_RUN_UNTIL_BREAKPOINT;
}
if (cpu.registers.PC == address) {
disasmHighlight.hit_pc = true;
}
return value;
}
tlm::tlm_response_status
Bus::write(const basic::addr_t &a, const basic::data_t &d)
{
// Testing the bypass
BASIC_TRACE_DEBUG("[!] CALL THE BUS'S WRITE FUNCTION [!]\n");
if(a % sizeof(basic::data_t)) {
SC_REPORT_ERROR(name(),
"unaligned write");
return tlm::TLM_ADDRESS_ERROR_RESPONSE;
}
addr_map_t::iterator it = addr_map.find(addr_range(a, a));
if(it == addr_map.end()) {
std::cerr << name() << ": no target at address " <<
std::hex << a << std::endl;
return tlm::TLM_ADDRESS_ERROR_RESPONSE;
}
#ifdef DEBUG
std::cout << "Debug: " << name() <<
": write access at 0x" << std::hex << a <<
" (data: 0x" << d << ")\n";
#endif
tlm::tlm_response_status s =
initiator.write(a - (*it).first.begin, d, (*it).second);
return s;
}
tlm::tlm_response_status
Bus::write(ensitlm::addr_t a, ensitlm::data_t d)
{
if(a % sizeof(ensitlm::data_t)) {
SC_REPORT_ERROR(name(),
"unaligned write");
return tlm::TLM_ADDRESS_ERROR_RESPONSE;
}
addr_map_t::iterator it = addr_map.find(addr_range(a, a));
if(it == addr_map.end()) {
std::cerr << name() << ": no target at address " <<
std::hex << a << std::endl;
return tlm::TLM_ADDRESS_ERROR_RESPONSE;
}
#ifdef DEBUG
std::cout << "Debug: " << name() <<
": write access at 0x" << std::hex << a <<
" (data: 0x" << d << ")\n";
#endif
tlm::tlm_response_status s =
initiator.write(a - (*it).first.begin, d, (*it).second);
return s;
}
bool
Bus::checkAdressRange(const basic::addr_t &a) {
addr_map_t::iterator it = addr_map.find(addr_range(a, a));
if(it==addr_map.end()) {
return true; // not in range
} else {
return false; // target available
}
}
void debug_write_byte(uint32_t address, uint8_t value) {
uint8_t *ptr;
address &= 0xFFFFFF;
if (address < 0xE00000) {
if ((ptr = phys_mem_ptr(address, 1))) {
*ptr = value;
}
} else {
debug_port_write_byte(mmio_range(address)<<12 | addr_range(address), value);
}
}
bool
Bus::checkAdressConcordance(basic::compatible_socket *target,
const basic::addr_t &a) {
addr_range range = addr_range(a, a);
for(port_map_t::iterator it = port_map.begin(); it != port_map.end(); ++it) {
addr_range current = (*it).second;
basic::compatible_socket *socket = (*it).first;
if(!(current<range) && !(range<current) && socket==target) {
//std::cout << " range : " << std::hex
//<< "[0x" << current.begin << "-0x" << current.end << "["
//<< std::endl;
return true;
}
}
return false;
}
void Bus::map(ensitlm::compatible_socket &port, ensitlm::addr_t start_addr,
ensitlm::addr_t size) {
port_map.insert(std::pair<ensitlm::compatible_socket *, addr_range>(
&port, addr_range(start_addr, start_addr + size - 1)));
}
void debug_port_write_byte(uint32_t address, uint8_t value) {
apb_map[port_range(address)].range->write_out(addr_range(address), value);
}
uint8_t debug_port_read_byte(uint32_t address) {
return apb_map[port_range(address)].range->read_in(addr_range(address));
}
