void InitPower(void)
{
uint32_t fcclk = 0;
uint32_t fsclk = 0;
uint32_t fvco = 0;
uint32_t core;
uint32_t system;
uint32_t expectedEvents;
ADI_PWR_RESULT result;
bError = false;
callbackEvents = 0;
expectedEvents = 0;
result = adi_pwr_Init(CLKIN, CORE_MAX, SYSTEM_MAX, VCO_MIN);
CheckResult(result);
// result = adi_pwr_InstallCallback(PWRCallback);
// CheckResult(result);
setDefaultPower();
// set max freq
result = adi_pwr_SetFreq(CORE_MAX, SYSTEM_MAX);
CheckResult(result);
expectedEvents += 2; //pre and post event
// get the freq settings
result = adi_pwr_GetCoreFreq(&fcclk);
CheckResult(result);
result = adi_pwr_GetSystemFreq(&fsclk);
CheckResult(result);
if ((fcclk < (CORE_MAX-CLKIN)) || (fsclk < (SYSTEM_MAX-CLKIN)))
{
bError = true;
}
system_parameters.fcclk = fcclk;
system_parameters.fsclk = fsclk;
}
ADI_UART_RESULT UARTx_IntMode_Init(int UARTx, long Baudrate, int Stopbit_Num, int Check_Mode, UART_Data_Struct* Uart_Struct)
{
ADI_UART_RESULT eResult = ADI_UART_FAILURE;
uint32_t div;
/* System Clock Frequencies*/
uint32_t fsysclk = 0u; /* System Clock */
uint32_t fsclk0 = 0u; /* System Clock0 */
uint32_t fsclk1 = 0u; /* System Clock1 */
/*初始化接收数据结构体*/
Uart_Struct->p_Buff_Start = Uart_Struct->Buff;
Uart_Struct->p_Buff_end = Uart_Struct->p_Buff_Start + Length_UART_BUFF - 512;//p_Buff_end后面需要留一部分512字节的长度用于缓存，这样可以减少环形节点的异常处理，提高效率
Uart_Struct->p_Buff_Read = Uart_Struct->p_Buff_Start;
Uart_Struct->p_Buff_Write = Uart_Struct->p_Buff_Start;
Uart_Struct->Num_Frame = 0;
Uart_Struct->flag = 0;
Uart_Struct->flag_Buff_Over = 0;
Uart_Struct->p_Buff_Tx_Start = Uart_Struct->Buff_Tx;
Uart_Struct->p_Buff_Tx = Uart_Struct->Buff_Tx;
Uart_Struct->flag_Tx_Finish = 0;
/* Initialize Power service */
if(adi_pwr_Init(myCLKIN, myCORE_MAX, mySYSCLK_MAX, myVCO_MIN) != ADI_PWR_SUCCESS)
{
printf("0x%08X :Failed to initialize power service \n", eResult);
}
if(adi_pwr_GetSystemFreq(&fsysclk, &fsclk0, &fsclk1) != ADI_PWR_SUCCESS)
{
return ADI_UART_SYSCLK_FAILED;
}
if( UARTx == UART0)
{
/* PORTx_MUX registers */
*pREG_PORTD_MUX |= UART0_TX_PORTD_MUX | UART0_RX_PORTD_MUX;
/* PORTx_FER registers */
*pREG_PORTD_FER |= UART0_TX_PORTD_FER | UART0_RX_PORTD_FER;
*pREG_UART0_CTL = 0;
*pREG_UART0_CTL |= UART_W8b;
switch ( Stopbit_Num )
{
case Onebit: break;
case Onehalfbit:*pREG_UART0_CTL |= UART_STBH;
break;
case twobit:*pREG_UART0_CTL |= UART_STB;
break;
case twohalfbit:*pREG_UART0_CTL |= UART_STB | UART_STBH;
break;
default:return ADI_UART_FAILURE;
}
switch ( Check_Mode )
{
case CHECK_PARITY_NO:break;
case CHECK_PARITY_ODD:*pREG_UART0_CTL |= UART_PEN;
break;
case CHECK_PARITY_EVEN: *pREG_UART0_CTL |= UART_PEN | UART_EPS;
break;
default:return ADI_UART_FAILURE;
}
//设置波特率
div = fsclk0 / Baudrate;
// *pREG_UART0_CLK=(((uint32_t)BIT31)|div); //Bit clock prescaler = 1
*pREG_UART0_CLK=(((uint32_t)BIT31)|div); //Bit clock prescaler = 1
//设置中断
adi_int_InstallHandler(80,IsrUart0Tx,Uart_Struct,true);
adi_int_InstallHandler(81,IsrUart0Rx,Uart_Struct,true);
*pREG_UART0_IMSK_SET |= BIT0; //允许接收中断
*pREG_UART0_CTL |= UART_EN; //使能串口
Uart0_T();
return ADI_UART_SUCCESS;
}else
{
/* PORTx_MUX registers */
*pREG_PORTG_MUX = UART1_TX_PORTG_MUX | UART1_RX_PORTG_MUX;
/* PORTx_FER registers */
*pREG_PORTG_FER = UART1_TX_PORTG_FER | UART1_RX_PORTG_FER;
*pREG_UART1_CTL = 0;
*pREG_UART1_CTL |= UART_W8b;
switch ( Stopbit_Num )
{
case Onebit: break;
case Onehalfbit:*pREG_UART1_CTL |= UART_STBH;
break;
case twobit:*pREG_UART1_CTL |= UART_STB;
break;
case twohalfbit:*pREG_UART1_CTL |= UART_STB | UART_STBH;
break;
default:return ADI_UART_FAILURE;
}
switch ( Check_Mode )
{
case CHECK_PARITY_NO:break;
case CHECK_PARITY_ODD:*pREG_UART1_CTL |= UART_PEN;
break;
case CHECK_PARITY_EVEN: *pREG_UART1_CTL |= UART_PEN | UART_EPS;
break;
default:return ADI_UART_FAILURE;
}
//设置波特率
div = fsysclk / Baudrate;
*pREG_UART1_CLK=(((uint32_t)BIT31)|div); //Bit clock prescaler = 1
//设置中断
adi_int_InstallHandler(83,IsrUart1Tx,Uart_Struct,true);
adi_int_InstallHandler(84,IsrUart1Rx,Uart_Struct,true);
*pREG_UART1_IMSK_SET |= BIT0; //允许接收中断
*pREG_UART1_CTL |= UART_EN; //使能串口
return ADI_UART_SUCCESS;
}
}
/**
* @brief Sets SPORT Device number to communicate with AD1854 instance.
*
* @param [in] hDevice AD1854 instance to work on.
* @param [in] SportDevNum SPORT Device number to use.
* @param [in] bExternalClk TRUE to source LRCLK and BCLK externally (operate SPORT as slave)
* FALSE to source LRCLK and BCLK from SPORT (operate SPORT as master)
*
* @return Status
* - #ADI_AD1854_SUCCESS: Successfully updated AD1854 settings.
* - #ADI_AD1854_BAD_HANDLE: Supplied Device handle is invalid.
* - #ADI_AD1854_ALREADY_RUNNING: Cannot perform this operation when dataflow is enabled.
* - #ADI_AD1854_SPORT_ERROR: SPORT Driver Error.
*
* @note Internal clock source from SPORT should be used with caution. Processor SCLK should be
* configured such that the SCLK frequency is a multiple of BCLK/LRCLK. This is required so that
* SPORT clock and FS divide register can be configured to generate the exact
* BCLK and LRCLK (48kHz) from SCLK.
*/
ADI_AD1854_RESULT adi_ad1854_SetSportDevice(
ADI_AD1854_HANDLE const hDevice,
uint32_t SportDevNum,
bool bExternalClk)
{
/* Control Register value */
uint16_t CtrlReg1, CtrlReg2;
/* Clock and FS div */
uint16_t TClkDiv, TFsDiv;
/* Location to hold SCLK freq */
uint32_t fsclk = 0u;
/* Pointer to AD1854 device instance to work on */
ADI_AD1854_DEV *pDevice = (ADI_AD1854_DEV *) hDevice;
/* IF (Debug information enabled) */
#if defined (ADI_DEBUG)
/* IF (AD1854 Handle is invalid) */
if (ValidateHandle (hDevice) != ADI_AD1854_SUCCESS)
{
return (ADI_AD1854_BAD_HANDLE);
}
#endif
/* IF (AD1854 dataflow enabled) */
if (pDevice->bIsEnabled)
{
/* Report failure as AD1854 is already running */
return (ADI_AD1854_ALREADY_RUNNING);
}
do
{
/* IF (SPORT Device is already open) */
if (pDevice->hSportDev)
{
/* Close the SPORT Device */
if (adi_sport_Close(pDevice->hSportDev) != ADI_SPORT_SUCCESS)
{
break;
}
/* Clear the SPORT Device handle */
pDevice->hSportDev = NULL;
}
/* Open the SPORT Device */
if (adi_sport_Open (SportDevNum,
ADI_SPORT_DIR_TX,
ADI_SPORT_I2S_MODE,
&(pDevice->SportDevMem[0]),
ADI_SPORT_DMA_MEMORY_SIZE,
&(pDevice->hSportDev)) != ADI_SPORT_SUCCESS)
{
break;
}
/*-- Configure SPORT driver --*/
/* IF (External Clock Source, SPORT is the Slave) */
if (bExternalClk)
{
/* SPORT Tx Control register 1 */
CtrlReg1 = ADI_AD1854_SPORT_SLAVE_TX_CTRL1;
/* SPORT Tx Control register 2 */
CtrlReg2 = ADI_AD1854_SPORT_SLAVE_TX_CTRL2;
}
/* ELSE (Source clock from SPORT, SPORT is Master) */
else
{
/* SPORT Tx Control register 1 */
CtrlReg1 = ADI_AD1854_SPORT_MASTER_TX_CTRL1;
/* SPORT Tx Control register 2 */
CtrlReg2 = ADI_AD1854_SPORT_MASTER_TX_CTRL2;
/* Get current SCLK */
if ((uint32_t)adi_pwr_GetSystemFreq(&fsclk) != 0u)
{
/* Return error as failed to configure SPORT */
break;
}
/* Calculate TCLKDIV */
/* TSCLKx frequency = (SCLK frequency)/(2 x (SPORTx_TCLKDIV + 1)) */
/* SPORTx_TCLKDIV = ((SCLK frequency) / (2 x TSCLKx frequency)) - 1 */
TClkDiv = (uint16_t) ((fsclk / AD1854_TCLK_FREQX2) - 1u);
/* Calculate TFSDIV */
/* SPORTxTFS frequency = (TSCLKx frequency)/(SPORTx_TFSDIV + 1) */
/* SPORTx_TFSDIV = ((TSCLKx frequency/SPORTxTFS) - 1) */
TFsDiv = (uint16_t) ((AD1854_TCLK_FREQ/AD1854_TFS_FREQ) - 1u);
/* Configure SPORTx_TCLKDIV register - Internal */
if (adi_sport_ConfigClock (pDevice->hSportDev, TClkDiv, true, true))
{
break;
}
/* Configure SPORTx_TFSDIV register - Internal */
if (adi_sport_ConfigFrameSync (pDevice->hSportDev, TFsDiv, true, true, true, false, false))
{
break;
}
}
/* Configure SPORT Tx Control register 1 */
if (adi_sport_SetControlReg (pDevice->hSportDev, ADI_SPORT_CONTROL_TX_REGISTER, CtrlReg1) != ADI_SPORT_SUCCESS)
{
break;
}
/* Configure SPORT Tx Control register 2 */
if (adi_sport_SetControlReg (pDevice->hSportDev, ADI_SPORT_CONTROL_TX_REGISTER2, CtrlReg2) != ADI_SPORT_SUCCESS)
{
break;
}
/* IF (we've a valid callback function) */
if (pDevice->pfCallback != NULL)
{
/* Pass a valid callback function to SPORT driver */
if (adi_sport_RegisterCallback (pDevice->hSportDev, SportCallback, pDevice) != ADI_SPORT_SUCCESS)
{
break;
}
}
/* Return Success */
return (ADI_AD1854_SUCCESS);
} while (0);
/* Return Failure */
return (ADI_AD1854_SPORT_ERROR);
}
