BDD Synth::get_bdd_for_sign_lit(uint lit) {
/* lit is an AIGER variable index with a 'sign' */
if (bdd_by_aiger_unlit.find(STRIP_LIT(lit)) != bdd_by_aiger_unlit.end()) {
BDD res = bdd_by_aiger_unlit[STRIP_LIT(lit)];
if (IS_NEGATED(lit))
return ~res;
}
uint stripped_lit = STRIP_LIT(lit);
BDD res;
if (stripped_lit == 0) {
res = cudd.bddZero();
}
else if (aiger_is_input(aiger_spec, stripped_lit) ||
aiger_is_latch(aiger_spec, stripped_lit)) {
res = cudd.ReadVars(cudd_by_aiger[stripped_lit]);
// MASSERT(res.NodeReadIndex() == stripped_lit/2, "that bug again: impossible: " << res.NodeReadIndex() << " vs " << stripped_lit/2 );
}
else { // aiger_and
aiger_and *and_ = aiger_is_and(aiger_spec, stripped_lit);
res = get_bdd_for_sign_lit(and_->rhs0) & get_bdd_for_sign_lit(and_->rhs1);
}
bdd_by_aiger_unlit[stripped_lit] = res;
return IS_NEGATED(lit) ? (~res):res;
}
static simpaig *
build_rec (unsigned lit)
{
unsigned sign = lit & 1;
unsigned idx = lit / 2;
simpaig *res, *l, *r;
aiger_and *and;
if (!(res = lois[idx].aig))
{
if (idx)
{
if ((and = aiger_is_and (model, 2 * idx)))
{
assert (and->lhs == 2 * idx);
l = build_rec (and->rhs0);
r = build_rec (and->rhs1);
res = simpaig_and (mgr, l, r);
}
else
res = simpaig_var (mgr, lois + idx, 0);
}
else
res = simpaig_false (mgr);
lois[idx].aig = res;
}
if (sign)
res = simpaig_not (res);
return res;
}
