/**
* This function will initial STM32 Radio board.
*/
void rt_hw_board_init(void)
{
/* Configure the system clocks */
SystemInit();
all_device_reset();
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the SysTick */
SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
/* Console Initialization*/
rt_hw_usart_init();
rt_console_set_device("uart1");
rt_kprintf("\r\n\r\nSystemInit......\r\n");
/* SPI1 config */
{
GPIO_InitTypeDef GPIO_InitStructure;
SPI_InitTypeDef SPI_InitStructure;
/* Enable SPI1 Periph clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
| RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
ENABLE);
/* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/*------------------------ SPI1 configuration ------------------------*/
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;/* 72M/64=1.125M */
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_I2S_DeInit(SPI1);
SPI_Init(SPI1, &SPI_InitStructure);
/* Enable SPI_MASTER */
SPI_Cmd(SPI1, ENABLE);
SPI_CalculateCRC(SPI1, DISABLE);
if (rt_sem_init(&spi1_lock, "spi1lock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
{
rt_kprintf("init spi1 lock semaphore failed\n");
}
}
}
/**
* This function will initial STM32 Radio board.
*/
void rt_hw_board_init(void)
{
/* Configure the system clocks */
SystemInit();
#ifndef STM32_SIMULATOR
all_device_reset();
#endif
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the SysTick */
SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
/* Console Initialization */
rt_hw_usart_init();
rt_console_set_device("uart1");
/* Led Initialization */
rt_hw_led_init();
rt_kprintf("\r\n\r\nSystemInit......\r\n");
}
void rt_hw_board_init(void)
{
//NAND_IDTypeDef NAND_ID;
/* Configure the system clocks */
SystemInit();
all_device_reset();
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the SysTick */
SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
/* Console Initialization*/
rt_hw_usart_init();
#if STM32_CONSOLE_USART == 1
rt_console_set_device("uart1");
#elif STM32_CONSOLE_USART == 2
rt_console_set_device("uart2");
#elif STM32_CONSOLE_USART == 3
rt_console_set_device("uart3");
#endif
up_mcu_show();
rt_kprintf("\r\n\r\nSystemInit......\r\n");
// show SN
{
uint8_t * sn = (uint8_t *)0x1FFFF7E8;
uint32_t i;
rt_kprintf("CPU SN: ");
for(i=0;i<12;i++)
{
rt_kprintf("%02X",*sn++);
}
rt_kprintf("\r\n");
}
/* SRAM init */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
FSMC_SRAM_Init();
/* memtest */
{
unsigned char * p_extram = (unsigned char *)STM32_EXT_SRAM_BEGIN;
unsigned int temp;
rt_kprintf("\r\nmem testing....");
for(temp=0; temp<(STM32_EXT_SRAM_END-STM32_EXT_SRAM_BEGIN); temp++)
{
*p_extram++ = (unsigned char)temp;
}
p_extram = (unsigned char *)STM32_EXT_SRAM_BEGIN;
for(temp=0; temp<(STM32_EXT_SRAM_END-STM32_EXT_SRAM_BEGIN); temp++)
{
if( *p_extram++ != (unsigned char)temp )
{
rt_kprintf("\rmemtest fail @ %08X\r\nsystem halt!!!!!",(unsigned int)p_extram);
while(1);
}
}
rt_kprintf("\rmem test pass!!\r\n");
}/* memtest */
}/* rt_hw_board_init */
void rt_hw_board_init(void)
{
//NAND_IDTypeDef NAND_ID;
/* Configure the system clocks */
SystemInit();
all_device_reset();
/* NVIC Configuration */
NVIC_Configuration();
/* Configure the SysTick */
SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
/* Console Initialization*/
rt_hw_usart_init();
#if STM32_CONSOLE_USART == 1
rt_console_set_device("uart1");
#elif STM32_CONSOLE_USART == 2
rt_console_set_device("uart2");
#elif STM32_CONSOLE_USART == 3
rt_console_set_device("uart3");
#endif
rt_kprintf("\r\n\r\nSystemInit......\r\n");
/* SRAM init */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
FSMC_SRAM_Init();
/* memtest */
{
unsigned char * p_extram = (unsigned char *)STM32_EXT_SRAM_BEGIN;
unsigned int temp;
rt_kprintf("\r\nmem testing....");
for(temp=0; temp<(STM32_EXT_SRAM_END-STM32_EXT_SRAM_BEGIN); temp++)
{
*p_extram++ = (unsigned char)temp;
}
p_extram = (unsigned char *)STM32_EXT_SRAM_BEGIN;
for(temp=0; temp<(STM32_EXT_SRAM_END-STM32_EXT_SRAM_BEGIN); temp++)
{
if( *p_extram++ != (unsigned char)temp )
{
rt_kprintf("\rmemtest fail @ %08X\r\nsystem halt!!!!!",(unsigned int)p_extram);
while(1);
}
}
rt_kprintf("\rmem test pass!!\r\n");
}/* memtest */
/* SPI1 config */
{
GPIO_InitTypeDef GPIO_InitStructure;
SPI_InitTypeDef SPI_InitStructure;
/* Enable SPI1 Periph clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
| RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
ENABLE);
/* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/*------------------------ SPI1 configuration ------------------------*/
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;/* 72M/64=1.125M */
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStructure.SPI_CRCPolynomial = 7;
SPI_I2S_DeInit(SPI1);
SPI_Init(SPI1, &SPI_InitStructure);
/* Enable SPI_MASTER */
SPI_Cmd(SPI1, ENABLE);
SPI_CalculateCRC(SPI1, DISABLE);
if (rt_sem_init(&spi1_lock, "spi1lock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
{
rt_kprintf("init spi1 lock semaphore failed\n");
}
}
}/* rt_hw_board_init */
