static void ambarella_wdt0_start(u32 mode)
{
if ((mode & WDOG_CTR_RST_EN) == WDOG_CTR_RST_EN) {
/* Allow the change of WDT_RST_L_REG via APB */
#if (RCT_SUPPORT_UNL_WDT_RST_ANAPWR == 1)
amba_writel(ANA_PWR_REG, readl(ANA_PWR_REG) | 0x80);
#endif
/* Clear the WDT_RST_L_REG to zero */
#if (RCT_WDT_RESET_VAL == 0)
amba_writel(WDT_RST_L_REG, RCT_WDT_RESET_VAL);
#else
amba_writel(WDT_RST_L_REG, 0x1);
#endif
/* Not allow the change of WDT_RST_L_REG via APB */
#if (RCT_SUPPORT_UNL_WDT_RST_ANAPWR == 1)
amba_writel(ANA_PWR_REG, readl(ANA_PWR_REG) & (~0x80));
#endif
/* Clear software reset bit. */
amba_writel(SOFT_RESET_REG, 0x2);
}
amba_writel(WDOG_CONTROL_REG, mode);
while(amba_tstbitsl(WDOG_CONTROL_REG, mode) != mode);
}
int fio_amb_sd2_is_enable(void)
{
return amba_tstbitsl(HOST_AHB_CLK_ENABLE_REG, HOST_AHB_SDIO_SEL);
}
int fio_amb_cf_is_enable(void)
{
return amba_tstbitsl(HOST_AHB_CLK_ENABLE_REG, HOST_AHB_CF_CLK_ENB);
}