static long efuse_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg )
{
switch (cmd)
{
#ifndef CONFIG_MESON_TRUSTZONE
case EFUSE_ENCRYPT_ENABLE:
aml_set_reg32_bits( P_EFUSE_CNTL4, CNTL4_ENCRYPT_ENABLE_ON,
CNTL4_ENCRYPT_ENABLE_BIT, CNTL4_ENCRYPT_ENABLE_SIZE);
break;
case EFUSE_ENCRYPT_DISABLE:
aml_set_reg32_bits( P_EFUSE_CNTL4, CNTL4_ENCRYPT_ENABLE_OFF,
CNTL4_ENCRYPT_ENABLE_BIT, CNTL4_ENCRYPT_ENABLE_SIZE);
break;
case EFUSE_ENCRYPT_RESET:
aml_set_reg32_bits( P_EFUSE_CNTL4, CNTL4_ENCRYPT_RESET_ON,
CNTL4_ENCRYPT_RESET_BIT, CNTL4_ENCRYPT_RESET_SIZE);
break;
#endif
case EFUSE_INFO_GET:
{
efuseinfo_item_t *info = (efuseinfo_item_t*)arg;
if(efuse_getinfo_byID(info->id, info) < 0)
return -EFAULT;
}
break;
default:
return -ENOTTY;
}
return 0;
}
void cec_hw_reset(void)
{
//unsigned long data32;
// Assert SW reset AO_CEC
//data32 = 0;
//data32 |= 0 << 1; // [2:1] cntl_clk: 0=Disable clk (Power-off mode); 1=Enable gated clock (Normal mode); 2=Enable free-run clk (Debug mode).
//data32 |= 1 << 0; // [0] sw_reset: 1=Reset
aml_write_reg32(P_AO_CEC_GEN_CNTL, 0x1);
// Enable gated clock (Normal mode).
aml_set_reg32_bits(P_AO_CEC_GEN_CNTL, 1, 1, 1);
// Release SW reset
aml_set_reg32_bits(P_AO_CEC_GEN_CNTL, 0, 0, 1);
// Enable all AO_CEC interrupt sources
if (!cec_int_disable_flag)
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 0x6, 0, 3);
aocec_wr_reg(CEC_LOGICAL_ADDR0, (0x1 << 4) | cec_global_info.my_node_index);
//Cec arbitration 3/5/7 bit time set.
cec_arbit_bit_time_set(3, 0x118, 0);
cec_arbit_bit_time_set(5, 0x000, 0);
cec_arbit_bit_time_set(7, 0x2aa, 0);
hdmi_print(INF, CEC "hw reset :logical addr:0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR0));
}
void set_vbyone_sync_pol(int hsync_pol, int vsync_pol)
{
aml_set_reg32_bits(P_VBO_VIN_CTRL,hsync_pol,VBO_VIN_HSYNC_POL_BIT,VBO_VIN_HSYNC_POL_WID);
aml_set_reg32_bits(P_VBO_VIN_CTRL,vsync_pol,VBO_VIN_VSYNC_POL_BIT,VBO_VIN_VSYNC_POL_WID);
aml_set_reg32_bits(P_VBO_VIN_CTRL,hsync_pol,VBO_VOUT_HSYNC_POL_BIT,VBO_VOUT_HSYNC_POL_WID);
aml_set_reg32_bits(P_VBO_VIN_CTRL,vsync_pol,VBO_VOUT_VSYNC_POL_BIT,VBO_VOUT_VSYNC_POL_WID);
}
static int ao_cec_ll_tx_polling(const unsigned char *msg, unsigned char len)
{
int i;
unsigned int ret = 0xf;
unsigned int n;
unsigned int j = 30;
while( aocec_rd_reg(CEC_TX_MSG_STATUS)){
if(TX_ERROR == aocec_rd_reg(CEC_TX_MSG_STATUS)){
//aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
//cec_hw_reset();
break;
}
if(!(j--)){
hdmi_print(INF, CEC "tx busy time out.\n");
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
}
msleep(5);
}
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 0x0, 1, 1);
for (i = 0; i < len; i++)
{
aocec_wr_reg(CEC_TX_MSG_0_HEADER + i, msg[i]);
}
aocec_wr_reg(CEC_TX_MSG_LENGTH, len-1);
aocec_wr_reg(CEC_TX_MSG_CMD, RX_ACK_CURRENT);
j = 30;
while((TX_DONE != aocec_rd_reg(CEC_TX_MSG_STATUS)) && (j--)){
if(TX_ERROR == aocec_rd_reg(CEC_TX_MSG_STATUS))
break;
msleep(5);
}
ret = aocec_rd_reg(CEC_TX_MSG_STATUS);
if(ret == TX_DONE)
ret = 1;
else
ret = 0;
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 1, 1, 1);
msleep(100);
if(cec_msg_dbg_en == 1) {
pos = 0;
pos += sprintf(msg_log_buf + pos, "CEC: tx msg len: %d dat: ", len);
for(n = 0; n < len; n++) {
pos += sprintf(msg_log_buf + pos, "%02x ", msg[n]);
}
pos += sprintf(msg_log_buf + pos, "\nCEC: tx state: %d\n", ret);
msg_log_buf[pos] = '\0';
printk("%s", msg_log_buf);
}
return ret;
}
void set_vbyone_ctlbits(int p3d_en, int p3d_lr, int mode)
{
if (mode == 0) //insert at the first pixel
aml_set_reg32_bits(P_VBO_PXL_CTRL,(1<<p3d_en)|(p3d_lr&0x1),VBO_PXL_CTR0_BIT,VBO_PXL_CTR0_WID);
else
aml_set_reg32_bits(P_VBO_VBK_CTRL_0,(1<<p3d_en)|(p3d_lr&0x1),0,2);
}
static void meson_gic_unmask(struct irq_data *data)
{
/**
* Set irq to edge rising and proi to low
*/
uint32_t dist_base=(uint32_t)(IO_PERIPH_BASE+0x1000);
int edge = 0x3;//edge
int irq=data->irq;
if(irq<32)
return;
/**
* USB A/B/C/D controller need level trig, This is temp code.
*
*/
if(irq == 62 || irq == 63 || irq == 100 || irq == 163 || irq == 164)
edge = 0x1;//level
/**
* set irq to edge rising .
*/
aml_set_reg32_bits(dist_base+GIC_DIST_CONFIG + (irq/16)*4,edge,(irq%16)*2,2);
/**
* Set prority
*/
#ifndef CONFIG_MESON6_SMP_HOTPLUG
aml_set_reg32_bits(dist_base+GIC_DIST_PRI + (irq / 4)* 4,0xff,(irq%4)*8,irq_level);
#endif
}
static void backlight_power_ctrl(Bool_t status)
{
PRINT_INFO("%s(): bl_status=%s, data_status=%s, bl_level=%u\n", __FUNCTION__, (bl_status ? "ON" : "OFF"), (data_status ? "ON" : "OFF"), bl_level);
if( status == ON ){
if ((bl_status == ON) || (data_status == OFF) || (bl_level == 0))
return;
aml_set_reg32_bits(P_LED_PWM_REG0, 1, 12, 2);
mdelay(20);
#if (BL_CTL==BL_CTL_GPIO)
//BL_EN -> GPIOD_1: 1
gpio_out(PAD_GPIOD_1, 1);
#elif (BL_CTL==BL_CTL_PWM)
aml_set_reg32_bits(P_PWM_MISC_REG_CD, PWM_PRE_DIV, 16, 7);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 23, 1);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 1, 1); //enable pwm_d
aml_write_reg32(P_PERIPHS_PIN_MUX_2, aml_read_reg32(P_PERIPHS_PIN_MUX_2) | (1<<3)); //enable pwm pinmux
#endif
}
else{
if (bl_status == OFF)
return;
#if (BL_CTL==BL_CTL_GPIO)
gpio_out(PAD_GPIOD_1, 0);
#elif (BL_CTL==BL_CTL_PWM)
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 0, 1, 1); //disable pwm_d
#endif
}
bl_status = status;
printk(KERN_INFO "%s() Power %s\n", __FUNCTION__, (status ? "ON" : "OFF"));
}
static int ao_cec_ll_rx( unsigned char *msg, unsigned char *len)
{
unsigned char i;
unsigned char data;
unsigned char n;
unsigned char *msg_start = msg;
unsigned int num;
int rx_msg_length;
int rx_status;
rx_status = aocec_rd_reg(CEC_RX_MSG_STATUS);
num = aocec_rd_reg(CEC_RX_NUM_MSG);
printk("rx irq:rx_status:0x%x:: num :0x%x\n", rx_status, num);
//aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 2, 1);
if(RX_DONE != rx_status){
printk("rx irq:!!!RX_DONE\n");
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return -1;
}
if(1 != num){
printk("rx irq:!!!num\n");
//aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
//aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
aocec_wr_reg(CEC_RX_CLEAR_BUF, 1);
aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 2, 1);
return -1;
}
rx_msg_length = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
for (i = 0; i < rx_msg_length && i < MAX_MSG; i++) {
data = aocec_rd_reg(CEC_RX_MSG_0_HEADER +i);
*msg = data;
msg++;
}
*len = rx_msg_length;
rx_status = aocec_rd_reg(CEC_RX_MSG_STATUS);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
//aocec_wr_reg(CEC_RX_CLEAR_BUF, 1);
aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 2, 1);
cec_hw_reset();
if(cec_msg_dbg_en == 1){
pos = 0;
pos += sprintf(msg_log_buf + pos, "CEC: rx msg len: %d dat: ", rx_msg_length);
for(n = 0; n < rx_msg_length; n++) {
pos += sprintf(msg_log_buf + pos, "%02x ", msg_start[n]);
}
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
hdmi_print(INF, CEC "%s", msg_log_buf);
}
return rx_status;
}
static void set_vid_clk_div(unsigned div)
{
check_clk_config(div);
if(div == 0)
div = 1;
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3); // select vid_pll_clk
aml_set_reg32_bits(P_HHI_VID_CLK_DIV, div-1, 0, 8);
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 7, 0, 3);
}
void set_ttl_pinmux(void)
{
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_0, 0x3f, 0, 6);
//aml_set_reg32_bits(P_PERIPHS_PIN_MUX_0, 0x3, 18, 2);
//aml_set_reg32_bits(P_PERIPHS_PIN_MUX_0, 0x1, 29, 1);
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_8, 0x7, 22, 3);
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_8, 0x1, 28, 1);
//aml_set_reg32_bits(P_PAD_PULL_UP_EN_REG4, 0x1, 26, 1);
//aml_set_reg32_bits(P_PAD_PULL_UP_REG4, 0x1, 26, 1);
}
static void ao_cec_sw_reset(void)
{
// Assert SW reset AO_CEC
//data32 = 0;
//data32 |= 0 << 1; // [2:1] cntl_clk: 0=Disable clk (Power-off mode); 1=Enable gated clock (Normal mode); 2=Enable free-run clk (Debug mode).
//data32 |= 1 << 0; // [0] sw_reset: 1=Reset
aml_write_reg32(P_AO_CEC_GEN_CNTL, 0x1);
// Enable gated clock (Normal mode).
aml_set_reg32_bits(P_AO_CEC_GEN_CNTL, 1, 1, 1);
// Release SW reset
aml_set_reg32_bits(P_AO_CEC_GEN_CNTL, 0, 0, 1);
}
static void hpll_load_en(void)
{
//hdmi load gen
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 7, 0 , 3);
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 1, 16, 3); // tmp use fclk_div4
aml_write_reg32(P_ENCL_VIDEO_EN, 0x1);
msleep(20);
aml_write_reg32(P_ENCL_VIDEO_EN, 0x0);
msleep(20);
// printk("read Addr: 0x%x[0x%x] Data: 0x%x\n", P_HHI_HDMI_PLL_CNTL, (P_HHI_HDMI_PLL_CNTL & 0xffff) >> 2, aml_read_reg32(P_HHI_HDMI_PLL_CNTL));
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3); // use vid_pll
}
static void gpio_set_vbus_power(char is_power_on)
{
if(is_power_on)
{
aml_set_reg32_bits(AOBUS_REG_ADDR(0x24), 0, 3, 1);
aml_set_reg32_bits(AOBUS_REG_ADDR(0x24), 0, 19, 1);
// aml_set_reg32_bits(AOBUS_REG_ADDR(0x24), 0, 2, 1);
// aml_set_reg32_bits(AOBUS_REG_ADDR(0x24), 1, 18, 1);
}
else
{
}
}
static void ao_cec_clk_set(void)
{
//AO CEC clock = 24M/732=32786.9Hz
//unsigned long data32;
//data32 = 0;
//data32 |= 1 << (10+16); // [26] clk_en
//data32 |= (732 - 1) << (0+16); // [25:16] clk_div
//*P_AO_CRT_CLK_CNTL1 = data32;
aml_set_reg32_bits(P_AO_CRT_CLK_CNTL1, 0, 16, 10);
aml_set_reg32_bits(P_AO_CRT_CLK_CNTL1, 1, 26, 1);
//aocec_wr_reg(CEC_CLOCK_DIV_L, (240-1)&0xff);
//aocec_wr_reg(CEC_CLOCK_DIV_H, ((240-1)>>8)&0xff);
}
void enable_crt_video_encl(int enable, int inSel)
{
aml_set_reg32_bits(P_HHI_VIID_CLK_DIV,inSel, 12, 4); //encl_clk_sel:hi_viid_clk_div[15:12]
if (inSel <= 4) //V1
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL,1, inSel, 1);
else
aml_set_reg32_bits(P_HHI_VIID_CLK_CNTL,1, (inSel-5),1);
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL2,enable, 3, 1); //gclk_encl_clk:hi_vid_clk_cntl2[3]
#ifndef NO_EDP_DSI
aml_set_reg32_bits(P_VPU_MISC_CTRL, 1, 0, 1); // vencl_clk_en_force: vpu_misc_ctrl[0]
#endif
}
static void _lcd_module_enable(void)
{
BUG_ON(pDev==NULL);
panel_oper.power_on();//panel power 12v
udelay(50);
_init_display_driver(&pDev->conf);//TX_clock
udelay(50);
////pull up pwm
aml_set_reg32_bits(P_PREG_PAD_GPIO1_O,0,30,1);
aml_set_reg32_bits(P_PREG_PAD_GPIO1_EN_N,1,30,1);
////pull up pwm
mdelay(160);
//_enable_backlight(BL_MAX_LEVEL); //disable backlight at pannel init
_enable_vsync_interrupt();
}
static void set_backlight_level(unsigned level)
{
mutex_lock(&bl_level_mutex);
PRINT_INFO(KERN_INFO "set_backlight_level: %u, last level: %u\n", level, bl_level);
level = (level > BL_MAX_LEVEL ? BL_MAX_LEVEL : (level < BL_MIN_LEVEL ? 0 : level));
bl_level = level;
if ((level == 0) && (bl_status == ON)) {
_power_off_backlight();
}
else {
if (level > BL_MID_LEVEL) {
level = ((level - BL_MID_LEVEL)*(BL_MAX_LEVEL-BL_MAPPED_MID_LEVEL))/(BL_MAX_LEVEL - BL_MID_LEVEL) + BL_MAPPED_MID_LEVEL;
} else {
//level = (level*BL_MAPPED_MID_LEVEL)/BL_MID_LEVEL;
level = ((level - BL_MIN_LEVEL)*(BL_MAPPED_MID_LEVEL - BL_MIN_LEVEL))/(BL_MID_LEVEL - BL_MIN_LEVEL) + BL_MIN_LEVEL;
}
#if (BL_CTL==BL_CTL_GPIO)
level = DIM_MIN - ((level - BL_MIN_LEVEL) * (DIM_MIN - DIM_MAX)) / (BL_MAX_LEVEL - BL_MIN_LEVEL);
aml_set_reg32_bits(P_LED_PWM_REG0, level, 0, 4);
#elif (BL_CTL==BL_CTL_PWM)
level = (PWM_MAX - PWM_MIN) * (level - BL_MIN_LEVEL) / (BL_MAX_LEVEL - BL_MIN_LEVEL) + PWM_MIN;
aml_write_reg32(P_PWM_PWM_D, (level << 16) | (PWM_CNT - level)); //pwm duty
#endif
if (bl_status == ON)
_power_on_backlight();
}
PRINT_INFO(KERN_INFO "set_backlight_level finished\n");
mutex_unlock(&bl_level_mutex);
}
static void set_backlight_level(unsigned level)
{
PRINT_INFO(KERN_INFO "set_backlight_level: %u, last level: %u\n", level, bl_level);
level = (level > BL_MAX_LEVEL ? BL_MAX_LEVEL : (level < BL_MIN_LEVEL ? 0 : level));
bl_level = level;
if (level == 0) {
backlight_power_ctrl(OFF);
}
else {
if (level > BL_MID_LEVEL) {
level = ((level - BL_MID_LEVEL)*(BL_MAX_LEVEL-BL_MAPPED_MID_LEVEL))/(BL_MAX_LEVEL - BL_MID_LEVEL) + BL_MAPPED_MID_LEVEL;
} else {
//level = (level*BL_MAPPED_MID_LEVEL)/BL_MID_LEVEL;
level = ((level - BL_MIN_LEVEL)*(BL_MAPPED_MID_LEVEL - BL_MIN_LEVEL))/(BL_MID_LEVEL - BL_MIN_LEVEL) + BL_MIN_LEVEL;
}
#if (BL_CTL==BL_CTL_GPIO)
level = DIM_MIN - ((level - BL_MIN_LEVEL) * (DIM_MIN - DIM_MAX)) / (BL_MAX_LEVEL - BL_MIN_LEVEL);
aml_set_reg32_bits(P_LED_PWM_REG0, level, 0, 4);
#elif (BL_CTL==BL_CTL_PWM)
level = (PWM_MAX - PWM_MIN) * (level - BL_MIN_LEVEL) / (BL_MAX_LEVEL - BL_MIN_LEVEL) + PWM_MIN;
aml_write_reg32(P_PWM_PWM_D, (level << 16) | (PWM_CNT - level)); //pwm duty
#endif
if (bl_status == OFF)
backlight_power_ctrl(ON);
}
}
void cec_disable_irq(void)
{
// disable all AO_CEC interrupt sources
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 0x0, 0, 3);
cec_int_disable_flag = 1;
hdmi_print(INF, CEC "disable:int mask:0x%x\n", aml_read_reg32(P_AO_CEC_INTR_MASKN));
}
// viu_channel_sel: 1 or 2
// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
int set_viu_path(unsigned viu_channel_sel, viu_type_e viu_type_sel)
{
if((viu_channel_sel > 2) || (viu_channel_sel == 0))
return -1;
printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", aml_read_reg32_d(P_VPU_VIU_VENC_MUX_CTRL));
if(viu_channel_sel == 1){
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
printk("viu chan = 1\n");
}
else{
//viu_channel_sel ==2
aml_set_reg32_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
printk("viu chan = 2\n");
}
printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", aml_read_reg32_d(P_VPU_VIU_VENC_MUX_CTRL));
return 0;
}
static inline void _disable_display_driver(Lcd_Config_t *pConf)
{
int vclk_sel;
vclk_sel = 0;//((pConf->lcd_timing.clk_ctrl) >>4) & 0x1;
aml_set_reg32_bits(P_HHI_VIID_DIVIDER_CNTL, 0, 11, 1); //close lvds phy clk gate: 0x104c[11]
aml_write_reg32(P_ENCT_VIDEO_EN, 0); //disable enct
aml_write_reg32(P_ENCL_VIDEO_EN, 0); //disable encl
if (vclk_sel)
aml_set_reg32_bits(P_HHI_VIID_CLK_CNTL, 0, 0, 5); //close vclk2 gate: 0x104b[4:0]
else
aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 0, 5); //close vclk1 gate: 0x105f[4:0]
printf("disable lcd display driver.\n");
}
// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
static void check_cts_hdmi_sys_clk_status(void)
{
int i;
for(i = 0; i < GATE_NUM; i++){
if(!(aml_read_reg32(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr)) & (1<<hdmi_gate[i].gate_bit))){
aml_set_reg32_bits(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr), 1, hdmi_gate[i].gate_bit, 1);
}
}
}
static void set_hpll_od3(unsigned div)
{
switch(div){
case 1:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 0, 18, 2);
break;
case 2:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 1, 18, 2);
break;
case 4:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 2, 18, 2);
break;
case 8:
aml_set_reg32_bits(P_HHI_HDMI_PLL_CNTL2, 3, 18, 2);
break;
default:
break;
}
}
static void set_hpll_lvds_od(unsigned div)
{
switch(div) {
case 1:
aml_set_reg32_bits(P_HHI_VID_PLL_CNTL, 0, 16, 2);
break;
case 2:
aml_set_reg32_bits(P_HHI_VID_PLL_CNTL, 1, 16, 2);
break;
case 4:
aml_set_reg32_bits(P_HHI_VID_PLL_CNTL, 2, 16, 2);
break;
case 8: // note: need test
aml_set_reg32_bits(P_HHI_VID_PLL_CNTL, 3, 16, 2);
break;
default:
break;
}
}
// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
static void check_cts_hdmi_sys_clk_status(void)
{
int i;
for(i = 0; i < GATE_NUM; i++){
if(!(aml_read_reg32(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr)) & (1<<hdmi_gate[i].gate_bit))){
printk("HDMI Gate Clock is off, turn on now\n");
aml_set_reg32_bits(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr), 1, hdmi_gate[i].gate_bit, 1);
}
}
}
int cec_ll_tx_polling(const unsigned char *msg, unsigned char len)
{
int i;
unsigned int ret = 0xf;
unsigned int n;
unsigned int j = 30;
int pos;
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 0x0, 1, 1);
for (i = 0; i < len; i++)
{
aocec_wr_reg(CEC_TX_MSG_0_HEADER + i, msg[i]);
}
aocec_wr_reg(CEC_TX_MSG_LENGTH, len-1);
aocec_wr_reg(CEC_TX_MSG_CMD, RX_ACK_CURRENT);
while((TX_DONE != aocec_rd_reg(CEC_TX_MSG_STATUS)) && (j--)){
msleep(5);
}
ret = aocec_rd_reg(CEC_TX_MSG_STATUS);
if(ret == TX_DONE)
ret = 1;
else
ret = 0;
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
aml_set_reg32_bits(P_AO_CEC_INTR_MASKN, 1, 1, 1);
if(cec_msg_dbg_en == 1) {
pos = 0;
pos += sprintf(msg_log_buf + pos, "CEC: tx msg len: %d dat: ", len);
for(n = 0; n < len; n++) {
pos += sprintf(msg_log_buf + pos, "%02x ", msg[n]);
}
pos += sprintf(msg_log_buf + pos, "\nCEC: tx state: %d\n", ret);
msg_log_buf[pos] = '\0';
printk("%s", msg_log_buf);
}
return ret;
}
static void set_control_vbyone(Lcd_Config_t *pConf)
{
int lane, byte, region, hsize, vsize;//color_fmt,
int vin_color, vin_bpp;
hsize = 3840;//pConf->lcd_basic.h_active;
vsize = 2160;//pConf->lcd_basic.v_active;
lane = 8;//byte_num;
byte = 4;//byte_num;
region = 2;//region_num;
vin_color = 4;
vin_bpp = 0;
printf("Set VbyOne PIN MUX ......\n");
aml_set_reg32_bits(P_PERIPHS_PIN_MUX_3,3,8,2);
// set Vbyone
printf("VbyOne Configuration ......\n");
//set_vbyone_vfmt(vin_color,vin_bpp);
aml_set_reg32_bits(P_VBO_VIN_CTRL, vin_color, VBO_VIN_PACK_BIT,VBO_VIN_PACK_WID);
aml_set_reg32_bits(P_VBO_VIN_CTRL,vin_bpp, VBO_VIN_BPP_BIT,VBO_VIN_BPP_WID);
config_vbyone(lane, byte, region, hsize, vsize);
set_vbyone_sync_pol(0, 0); //set hsync/vsync polarity to let the polarity is low active inside the VbyOne
// below line copy from simulation
aml_set_reg32_bits(P_VBO_VIN_CTRL, 1, 0, 2); //gate the input when vsync asserted
///aml_set_reg32(P_VBO_VBK_CTRL_0,0x13);
//aml_set_reg32(P_VBO_VBK_CTRL_1,0x56);
//aml_set_reg32(P_VBO_HBK_CTRL,0x3478);
//aml_set_reg32_bits(P_VBO_PXL_CTRL,0x2,VBO_PXL_CTR0_BIT,VBO_PXL_CTR0_WID);
//aml_set_reg32_bits(P_VBO_PXL_CTRL,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
//set_vbyone_ctlbits(1,0,0);
//set fifo_clk_sel: 3 for 10-bits
aml_set_reg32_bits(P_HHI_LVDS_TX_PHY_CNTL0,3,6,2);
//PAD select:
if ((lane == 1) || (lane == 2)) {
aml_set_reg32_bits(P_LCD_PORT_SWAP,1,9,2);
} else if (lane == 4) {
aml_set_reg32_bits(P_LCD_PORT_SWAP,2,9,2);
} else {
aml_set_reg32_bits(P_LCD_PORT_SWAP,0,9,2);
}
//aml_set_reg32_bits(P_LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order
// Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp
aml_write_reg32(P_HHI_DSI_LVDS_EDP_CNTL0, 0x1); // Select vbyone in combo-phy
aml_set_reg32_bits(P_VBO_CTRL_L, 1, VBO_ENABLE_BIT, VBO_EBABLE_WID);
//force vencl clk enable, otherwise, it might auto turn off by mipi DSI
printf("VbyOne is In Normal Status ......\n");
}
void vpp_set_matrix_ycbcr2rgb (int vd1_or_vd2_or_post, int mode)
{
if (vd1_or_vd2_or_post == 0) { //vd1
aml_set_reg32_bits (P_VPP_MATRIX_CTRL, 1, 5, 1);
aml_set_reg32_bits (P_VPP_MATRIX_CTRL, 1, 8, 2);
}else if (vd1_or_vd2_or_post == 1) { //vd2
aml_set_reg32_bits (P_VPP_MATRIX_CTRL, 1, 4, 1);
aml_set_reg32_bits (P_VPP_MATRIX_CTRL, 2, 8, 2);
}else{
aml_set_reg32_bits (P_VPP_MATRIX_CTRL, 1, 0, 1);
aml_set_reg32_bits (P_VPP_MATRIX_CTRL, 0, 8, 2);
if (mode == 0) {
aml_set_reg32_bits(P_VPP_MATRIX_CTRL, 1, 1, 2);
}else if (mode == 1) {
aml_set_reg32_bits(P_VPP_MATRIX_CTRL, 0, 1, 2);
}
}
if (mode == 0) { //ycbcr not full range, 601 conversion
aml_write_reg32(P_VPP_MATRIX_PRE_OFFSET0_1, 0x0064C8FF);
aml_write_reg32(P_VPP_MATRIX_PRE_OFFSET2, 0x006400C8);
//1.164 0 1.596
//1.164 -0.392 -0.813
//1.164 2.017 0
aml_write_reg32(P_VPP_MATRIX_COEF00_01, 0x04000000);
aml_write_reg32(P_VPP_MATRIX_COEF02_10, 0x059C0400);
aml_write_reg32(P_VPP_MATRIX_COEF11_12, 0x1EA01D24);
aml_write_reg32(P_VPP_MATRIX_COEF20_21, 0x04000718);
aml_write_reg32(P_VPP_MATRIX_COEF22, 0x00000000);
aml_write_reg32(P_VPP_MATRIX_OFFSET0_1, 0x00000000);
aml_write_reg32(P_VPP_MATRIX_OFFSET2, 0x00000000);
aml_write_reg32(P_VPP_MATRIX_PRE_OFFSET0_1, 0x00000E00);
aml_write_reg32(P_VPP_MATRIX_PRE_OFFSET2, 0x00000E00);
}else if (mode == 1) {//ycbcr full range, 601 conversion
aml_write_reg32(P_VPP_MATRIX_PRE_OFFSET0_1, 0x0000600);
aml_write_reg32(P_VPP_MATRIX_PRE_OFFSET2, 0x0600);
//1 0 1.402
//1 -0.34414 -0.71414
//1 1.772 0
aml_write_reg32(P_VPP_MATRIX_COEF00_01, (0x400 << 16) |0);
aml_write_reg32(P_VPP_MATRIX_COEF02_10, (0x59c << 16) |0x400);
aml_write_reg32(P_VPP_MATRIX_COEF11_12, (0x1ea0 << 16) |0x1d25);
aml_write_reg32(P_VPP_MATRIX_COEF20_21, (0x400 << 16) |0x717);
aml_write_reg32(P_VPP_MATRIX_COEF22, 0x0);
aml_write_reg32(P_VPP_MATRIX_OFFSET0_1, 0x0);
aml_write_reg32(P_VPP_MATRIX_OFFSET2, 0x0);
}
}
static vmode_t nulldisp_validate_vmode(char *mode)
{
const vinfo_t *info = get_valid_vinfo(mode);
int viu1_select = aml_read_reg32(P_VPU_VIU_VENC_MUX_CTRL)&0x3;
DisableVideoLayer();
aml_set_reg32_bits (P_VPU_VIU_VENC_MUX_CTRL, (viu1_select+1)&0x3, 2, 2); //viu2_select should be different from viu1_select (to fix viu1 video smooth problem)
if (info)
return info->mode;
return VMODE_MAX;
}
static inline void _power_on_backlight(void)
{
mutex_lock(&bl_power_mutex);
if (bl_real_status) {
mutex_unlock(&bl_power_mutex);
return;
}
aml_set_reg32_bits(P_LED_PWM_REG0, 1, 12, 2);
lcd_mdelay(20);
#if (BL_CTL==BL_CTL_GPIO)
//BL_EN -> GPIOD_1: 1
gpio_out(PAD_GPIOD_1, 1);
#elif (BL_CTL==BL_CTL_PWM)
gpio_out(PAD_GPIOC_8, 1);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, PWM_PRE_DIV, 16, 7);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 23, 1);
aml_set_reg32_bits(P_PWM_MISC_REG_CD, 1, 1, 1); //enable pwm_d
aml_write_reg32(P_PERIPHS_PIN_MUX_2, aml_read_reg32(P_PERIPHS_PIN_MUX_2) | (1<<3)); //enable pwm pinmux
#endif
bl_real_status = 1;
mutex_unlock(&bl_power_mutex);
}
