sw_error_t sw_uk_init(a_uint32_t nl_prot) { if (!nl_hdr) { nl_hdr = (struct nlmsghdr *)aos_mem_alloc(NLMSG_SPACE(SW_MAX_PAYLOAD)); } if (!nl_hdr) { return SW_NO_RESOURCE; } ssdk_sock_prot = nl_prot; SOCK_LOCKER_INIT; aos_mem_zero(ssdk_sock, sizeof(ssdk_sock_t) * SSDK_SOCK_FD_NUM); return SW_OK; }
sw_error_t athena_vlan_init(a_uint32_t dev_id) { #ifdef HSL_STANDALONG a_int16_t i; v_array_t *p_v_array; v_array_t *p_mem; HSL_DEV_ID_CHECK(dev_id); /* allocate memory for vlan info */ p_mem = aos_mem_alloc(MAX_VLAN_ENTRY * (sizeof (v_array_t))); if (p_mem == NULL) return SW_OUT_OF_MEM; aos_mem_zero(p_mem, MAX_VLAN_ENTRY * (sizeof (v_array_t))); /* start address for vlan info */ p_vlan_table[dev_id] = p_v_array = p_mem; for (i = 0; i < MAX_VLAN_ENTRY; i++) { p_v_array[i].active = A_FALSE; } #endif #ifndef HSL_STANDALONG hsl_api_t *p_api; SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); p_api->vlan_entry_append = athena_vlan_entry_append; p_api->vlan_creat = athena_vlan_create; p_api->vlan_delete = athena_vlan_delete; #endif return SW_OK; }
sw_error_t hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) { sw_error_t rv = SW_OK; if (SW_MAX_NR_DEV <= dev_id) { return SW_BAD_PARAM; } aos_mem_set(&dev_table[dev_id], 0, sizeof (hsl_dev_t)); SW_RTN_ON_ERROR(sd_init(dev_id,cfg)); #ifdef UK_IF SW_RTN_ON_ERROR(sw_uk_init(cfg->nl_prot)); #endif #if defined API_LOCK SW_RTN_ON_ERROR(hsl_api_lock_init()); #endif rv = SW_INIT_ERROR; switch (cfg->chip_type) { case CHIP_ATHENA: #if defined ATHENA rv = athena_init(dev_id, cfg); #endif break; case CHIP_GARUDA: #if defined GARUDA rv = garuda_init(dev_id, cfg); #endif break; case CHIP_SHIVA: #if defined SHIVA rv = shiva_init(dev_id, cfg); #endif break; case CHIP_HORUS: #if defined HORUS rv = horus_init(dev_id, cfg); #endif break; case CHIP_ISIS: #if defined ISIS rv = isis_init(dev_id, cfg); #endif break; case CHIP_ISISC: #if defined ISISC rv = isis_init(dev_id, cfg); #endif break; case CHIP_UNSPECIFIED: #if defined ATHENA rv = athena_init(dev_id, cfg); #elif defined GARUDA rv = garuda_init(dev_id, cfg); #elif defined SHIVA rv = shiva_init(dev_id, cfg); #elif defined HORUS rv = horus_init(dev_id, cfg); #elif defined ISIS rv = isis_init(dev_id, cfg); #elif defined ISISC rv = isis_init(dev_id, cfg); #endif break; default: return SW_BAD_PARAM; } SW_RTN_ON_ERROR(rv); if (NULL == dev_ssdk_cfg[dev_id]) { dev_ssdk_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); } if (NULL == dev_ssdk_cfg[dev_id]) { return SW_OUT_OF_MEM; } aos_mem_copy(dev_ssdk_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); #if defined UK_MINOR_DEV dev_ssdk_cfg[dev_id]->nl_prot = UK_MINOR_DEV; #endif return rv; }
/** * @brief Init hsl layer. * @details Comments: * This operation will init hsl layer and hsl layer * @param[in] dev_id device id * @param[in] cfg configuration for initialization * @return SW_OK or error code */ sw_error_t isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) { HSL_DEV_ID_CHECK(dev_id); if (NULL == isis_cfg[dev_id]) { isis_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); } if (NULL == isis_cfg[dev_id]) { return SW_OUT_OF_MEM; } aos_mem_copy(isis_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); SW_RTN_ON_ERROR(isis_reg_access_init(dev_id, cfg->reg_mode)); SW_RTN_ON_ERROR(isis_dev_init(dev_id, cfg->cpu_mode)); #if !(defined(KERNEL_MODULE) && defined(USER_MODE)) { sw_error_t rv; SW_RTN_ON_ERROR(hsl_port_prop_init()); SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); SW_RTN_ON_ERROR(isis_portproperty_init(dev_id, cfg->cpu_mode)); ISIS_MIB_INIT(rv, dev_id); ISIS_PORT_CTRL_INIT(rv, dev_id); ISIS_PORTVLAN_INIT(rv, dev_id); ISIS_VLAN_INIT(rv, dev_id); ISIS_FDB_INIT(rv, dev_id); ISIS_QOS_INIT(rv, dev_id); ISIS_STP_INIT(rv, dev_id); ISIS_MIRR_INIT(rv, dev_id); ISIS_RATE_INIT(rv, dev_id); ISIS_MISC_INIT(rv, dev_id); ISIS_LEAKY_INIT(rv, dev_id); ISIS_IGMP_INIT(rv, dev_id); ISIS_ACL_INIT(rv, dev_id); ISIS_LED_INIT(rv, dev_id); ISIS_COSMAP_INIT(rv, dev_id); ISIS_IP_INIT(rv, dev_id); ISIS_NAT_INIT(rv, dev_id); ISIS_TRUNK_INIT(rv, dev_id); ISIS_SEC_INIT(rv, dev_id); ISIS_INTERFACE_CTRL_INIT(rv, dev_id); { hsl_api_t *p_api; SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); p_api->dev_reset = isis_reset; p_api->dev_clean = isis_cleanup; } SW_RTN_ON_ERROR(isis_hw_init(dev_id, cfg)); #if defined(IN_NAT_HELPER) ISIS_NAT_HELPER_INIT(rv, dev_id); #endif } #endif return SW_OK; }
sw_error_t isis_acl_init(a_uint32_t dev_id) { HSL_DEV_ID_CHECK(dev_id); sw_list_ent[dev_id] = (isis_acl_list_t *) aos_mem_alloc(ISIS_MAX_FILTER * sizeof (isis_acl_list_t)); if (NULL == sw_list_ent[dev_id]) { return SW_NO_RESOURCE; } aos_mem_zero(sw_list_ent[dev_id], ISIS_MAX_FILTER * sizeof (isis_acl_list_t)); sw_rule_ent[dev_id] = (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); if (NULL == sw_rule_ent[dev_id]) { return SW_NO_RESOURCE; } aos_mem_zero(sw_rule_ent[dev_id], ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); hw_rule_tmp[dev_id] = (isis_acl_rule_t *) aos_mem_alloc(ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t)); if (NULL == hw_rule_tmp[dev_id]) { return SW_NO_RESOURCE; } sw_rule_tmp[dev_id] = (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); if (NULL == sw_rule_tmp[dev_id]) { return SW_NO_RESOURCE; } #ifdef ISIS_SW_ENTRY sw_filter_mem = aos_mem_alloc(ISIS_MAX_FILTER * sizeof (hw_filter_t)); if (NULL == sw_filter_mem) { return SW_NO_RESOURCE; } aos_mem_zero(sw_filter_mem, ISIS_MAX_FILTER * sizeof (hw_filter_t)); #endif #ifndef HSL_STANDALONG { hsl_api_t *p_api; SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); p_api->acl_list_creat = isis_acl_list_creat; p_api->acl_list_destroy = isis_acl_list_destroy; p_api->acl_list_bind = isis_acl_list_bind; p_api->acl_list_unbind = isis_acl_list_unbind; p_api->acl_rule_add = isis_acl_rule_add; p_api->acl_rule_delete = isis_acl_rule_delete; p_api->acl_rule_query = isis_acl_rule_query; p_api->acl_status_set = isis_acl_status_set; p_api->acl_status_get = isis_acl_status_get; p_api->acl_list_dump = isis_acl_list_dump; p_api->acl_rule_dump = isis_acl_rule_dump; p_api->acl_port_udf_profile_set = isis_acl_port_udf_profile_set; p_api->acl_port_udf_profile_get = isis_acl_port_udf_profile_get; } #endif return SW_OK; }
/** * @brief Init hsl layer. * @details Comments: * This operation will init hsl layer and hsl layer * @param[in] dev_id device id * @param[in] cfg configuration for initialization * @return SW_OK or error code */ sw_error_t garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) { a_uint8_t *p_mem; HSL_DEV_ID_CHECK(dev_id); p_mem = (a_uint8_t *)garuda_cfg[dev_id]; if (NULL == p_mem) { p_mem = aos_mem_alloc(sizeof (ssdk_init_cfg) + sizeof(garuda_init_spec_cfg)); garuda_cfg[dev_id] = (ssdk_init_cfg *)p_mem; garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *) (p_mem + sizeof (ssdk_init_cfg)); } if (NULL == p_mem) { return SW_OUT_OF_MEM; } aos_mem_copy(garuda_cfg[dev_id]->chip_spec_cfg, cfg->chip_spec_cfg, sizeof (garuda_init_spec_cfg)); aos_mem_copy(garuda_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *) (p_mem + sizeof (ssdk_init_cfg)); SW_RTN_ON_ERROR(garuda_reg_access_init(dev_id, cfg->reg_mode)); SW_RTN_ON_ERROR(garuda_dev_init(dev_id, cfg->cpu_mode)); #if !(defined(KERNEL_MODULE) && defined(USER_MODE)) { a_uint32_t i, entry; sw_error_t rv; if(HSL_MDIO == cfg->reg_mode) { SW_RTN_ON_ERROR(garuda_bist_test(dev_id)); entry = 0x1; HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); i = 0x10; do { HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_mdelay(10); } while (entry && --i); if (0 == i) { return SW_INIT_ERROR; } } SW_RTN_ON_ERROR(hsl_port_prop_init()); SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); SW_RTN_ON_ERROR(garuda_portproperty_init(dev_id, cfg->cpu_mode)); GARUDA_MIB_INIT(rv, dev_id); GARUDA_PORT_CTRL_INIT(rv, dev_id); GARUDA_PORTVLAN_INIT(rv, dev_id); GARUDA_VLAN_INIT(rv, dev_id); GARUDA_FDB_INIT(rv, dev_id); GARUDA_QOS_INIT(rv, dev_id); GARUDA_STP_INIT(rv, dev_id); GARUDA_MIRR_INIT(rv, dev_id); GARUDA_RATE_INIT(rv, dev_id); GARUDA_MISC_INIT(rv, dev_id); GARUDA_LEAKY_INIT(rv, dev_id); GARUDA_IGMP_INIT(rv, dev_id); GARUDA_ACL_INIT(rv, dev_id); GARUDA_LED_INIT(rv, dev_id); { hsl_api_t *p_api; SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); p_api->dev_reset = garuda_reset; p_api->dev_clean = garuda_cleanup; } if(cfg->reg_mode == HSL_MDIO) { SW_RTN_ON_ERROR(garuda_hw_init(dev_id, cfg)); } } #endif return SW_OK; }
/** * @brief Init hsl layer. * @details Comments: * This operation will init hsl layer and hsl layer * @param[in] dev_id device id * @param[in] cfg configuration for initialization * @return SW_OK or error code */ sw_error_t horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) { HSL_DEV_ID_CHECK(dev_id); if (NULL == horus_cfg[dev_id]) { horus_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); } if (NULL == horus_cfg[dev_id]) { return SW_OUT_OF_MEM; } aos_mem_copy(horus_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); SW_RTN_ON_ERROR(horus_reg_access_init(dev_id, cfg->reg_mode)); SW_RTN_ON_ERROR(horus_dev_init(dev_id, cfg->cpu_mode)); #if !(defined(KERNEL_MODULE) && defined(USER_MODE)) { a_uint32_t i, entry; sw_error_t rv; SW_RTN_ON_ERROR(horus_bist_test(dev_id)); entry = 0x1; HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); i = 0x10; do { HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); SW_RTN_ON_ERROR(rv); aos_mdelay(10); } while (entry && --i); if (0 == i) { return SW_INIT_ERROR; } SW_RTN_ON_ERROR(hsl_port_prop_init()); SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); SW_RTN_ON_ERROR(horus_portproperty_init(dev_id, cfg->cpu_mode)); HORUS_MIB_INIT(rv, dev_id); HORUS_PORT_CTRL_INIT(rv, dev_id); HORUS_PORTVLAN_INIT(rv, dev_id); HORUS_VLAN_INIT(rv, dev_id); HORUS_FDB_INIT(rv, dev_id); HORUS_QOS_INIT(rv, dev_id); HORUS_STP_INIT(rv, dev_id); HORUS_MIRR_INIT(rv, dev_id); HORUS_RATE_INIT(rv, dev_id); HORUS_MISC_INIT(rv, dev_id); HORUS_LEAKY_INIT(rv, dev_id); HORUS_IGMP_INIT(rv, dev_id); HORUS_LED_INIT(rv, dev_id); { hsl_api_t *p_api; SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); p_api->dev_reset = horus_reset; p_api->dev_clean = horus_cleanup; } SW_RTN_ON_ERROR(horus_hw_init(dev_id, cfg)); } #endif return SW_OK; }