const char* ARMv7DOpcodeDataProcessingRegisterT1::format()
{
appendInstructionName(opName(), inITBlock() && (!(op() == 0x8) || (op() == 0xa) || (op() == 0xb)));
appendRegisterName(rdn());
appendSeparator();
appendRegisterName(rm());
if (op() == 0x9) // rsb T1
appendString(", #0");
else if (op() == 0xd) { // mul T1
appendSeparator();
appendRegisterName(rdn());
}
return m_formatBuffer;
}
const char* ARMv7DOpcodeBranchConditionalT1::format()
{
if (condition() == 0xe)
return defaultFormat();
if (condition() == 0xf) {
appendInstructionName("svc");
appendUnsignedImmediate(offset());
return m_formatBuffer;
}
bufferPrintf(" b%-6.6s", conditionName(condition()));
appendPCRelativeOffset(static_cast<int32_t>(offset()) + 2);
return m_formatBuffer;
}
const char* ARMv7DOpcodeLoadStoreRegisterImmediate::format()
{
const char* instructionName = opName();
if (!instructionName)
return defaultFormat();
appendInstructionName(opName());
appendRegisterName(rt());
appendSeparator();
appendCharacter('[');
appendRegisterName(rn());
if (immediate5()) {
appendSeparator();
appendUnsignedImmediate(immediate5() << scale());
}
appendCharacter(']');
return m_formatBuffer;
}
