/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar2316SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
for (i = 0; i < N(ar5212Bank##_ix##_2316); i++) \
(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];\
} while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t ob2GHz = 0, db2GHz = 0;
struct ar2316State *priv = AR2316(ah);
int regWrites = 0;
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
__func__, chan->ic_freq, chan->ic_flags, modesIndex);
HALASSERT(priv != AH_NULL);
/* Setup rf parameters */
if (IEEE80211_IS_CHAN_B(chan)) {
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
} else {
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
}
/* Bank 1 Write */
RF_BANK_SETUP(priv, 1, 1);
/* Bank 2 Write */
RF_BANK_SETUP(priv, 2, modesIndex);
/* Bank 3 Write */
RF_BANK_SETUP(priv, 3, modesIndex);
/* Bank 6 Write */
RF_BANK_SETUP(priv, 6, modesIndex);
ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 178, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 175, 0);
/* Bank 7 Setup */
RF_BANK_SETUP(priv, 7, modesIndex);
/* Write Analog registers */
HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
#undef RF_BANK_SETUP
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, u_int16_t modesIndex, u_int16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_pb, _ix, _col) do { \
int i; \
for (i = 0; i < N(ar5212Bank##_ix##_2316); i++) \
(_pb)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];\
} while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
u_int16_t ob2GHz = 0, db2GHz = 0;
AR5212_RF_BANKS_2316 *pRfBanks;
int regWrites = 0;
HDPRINTF(ah, HAL_DBG_CHANNEL, "==>%s:chan 0x%x flag 0x%x modesIndex 0x%x\n",
__func__, chan->channel, chan->channelFlags, modesIndex);
pRfBanks = ahp->ah_analogBanks;
HALASSERT(pRfBanks);
/* Setup rf parameters */
switch (chan->channelFlags & CHANNEL_ALL) {
case CHANNEL_B:
ob2GHz = ahp->ah_obFor24;
db2GHz = ahp->ah_dbFor24;
break;
case CHANNEL_G:
case CHANNEL_108G:
ob2GHz = ahp->ah_obFor24g;
db2GHz = ahp->ah_dbFor24g;
break;
default:
HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid channel flags 0x%x\n",
__func__, chan->channelFlags);
return AH_FALSE;
}
/* Bank 1 Write */
RF_BANK_SETUP(pRfBanks, 1, 1);
/* Bank 2 Write */
RF_BANK_SETUP(pRfBanks, 2, modesIndex);
/* Bank 3 Write */
RF_BANK_SETUP(pRfBanks, 3, modesIndex);
/* Bank 6 Write */
RF_BANK_SETUP(pRfBanks, 6, modesIndex);
ar5212ModifyRfBuffer(pRfBanks->Bank6Data, ob2GHz, 3, 178, 0);
ar5212ModifyRfBuffer(pRfBanks->Bank6Data, db2GHz, 3, 175, 0);
/* Bank 7 Setup */
RF_BANK_SETUP(pRfBanks, 7, modesIndex);
/* Write Analog registers */
REG_WRITE_RF_ARRAY(ar5212Bank1_2316, pRfBanks->Bank1Data, regWrites);
REG_WRITE_RF_ARRAY(ar5212Bank2_2316, pRfBanks->Bank2Data, regWrites);
REG_WRITE_RF_ARRAY(ar5212Bank3_2316, pRfBanks->Bank3Data, regWrites);
REG_WRITE_RF_ARRAY(ar5212Bank6_2316, pRfBanks->Bank6Data, regWrites);
REG_WRITE_RF_ARRAY(ar5212Bank7_2316, pRfBanks->Bank7Data, regWrites);
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
#undef RF_BANK_SETUP
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
uint16_t modesIndex, uint16_t *rfXpdGain)
{
uint16_t freq = ath_hal_gethwchannel(ah, chan);
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
uint16_t tempOB, tempDB;
uint32_t ob2GHz, db2GHz, rfReg[NELEM(ar5212Bank6_5111)];
int i, regWrites = 0;
HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
__func__, chan->ic_freq, chan->ic_flags, modesIndex);
/* Setup rf parameters */
switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
case IEEE80211_CHAN_A:
if (4000 < freq && freq < 5260) {
tempOB = ee->ee_ob1;
tempDB = ee->ee_db1;
} else if (5260 <= freq && freq < 5500) {
tempOB = ee->ee_ob2;
tempDB = ee->ee_db2;
} else if (5500 <= freq && freq < 5725) {
tempOB = ee->ee_ob3;
tempDB = ee->ee_db3;
} else if (freq >= 5725) {
tempOB = ee->ee_ob4;
tempDB = ee->ee_db4;
} else {
/* XXX when does this happen??? */
tempOB = tempDB = 0;
}
ob2GHz = db2GHz = 0;
rfXpdGainFixed = ee->ee_xgain[headerInfo11A];
rfPloSel = ee->ee_xpd[headerInfo11A];
rfPwdXpd = !ee->ee_xpd[headerInfo11A];
gainI = ee->ee_gainI[headerInfo11A];
break;
case IEEE80211_CHAN_B:
tempOB = ee->ee_obFor24;
tempDB = ee->ee_dbFor24;
ob2GHz = ee->ee_ob2GHz[0];
db2GHz = ee->ee_db2GHz[0];
rfXpdGainFixed = ee->ee_xgain[headerInfo11B];
rfPloSel = ee->ee_xpd[headerInfo11B];
rfPwdXpd = !ee->ee_xpd[headerInfo11B];
gainI = ee->ee_gainI[headerInfo11B];
break;
case IEEE80211_CHAN_G:
case IEEE80211_CHAN_PUREG: /* NB: really 108G */
tempOB = ee->ee_obFor24g;
tempDB = ee->ee_dbFor24g;
ob2GHz = ee->ee_ob2GHz[1];
db2GHz = ee->ee_db2GHz[1];
rfXpdGainFixed = ee->ee_xgain[headerInfo11G];
rfPloSel = ee->ee_xpd[headerInfo11G];
rfPwdXpd = !ee->ee_xpd[headerInfo11G];
gainI = ee->ee_gainI[headerInfo11G];
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
__func__, chan->ic_flags);
return AH_FALSE;
}
HALASSERT(1 <= tempOB && tempOB <= 5);
HALASSERT(1 <= tempDB && tempDB <= 5);
/* Bank 0 Write */
for (i = 0; i < NELEM(ar5212Bank0_5111); i++)
rfReg[i] = ar5212Bank0_5111[i][modesIndex];
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
}
HAL_INI_WRITE_BANK(ah, ar5212Bank0_5111, rfReg, regWrites);
/* Bank 1 Write */
HAL_INI_WRITE_ARRAY(ah, ar5212Bank1_5111, 1, regWrites);
/* Bank 2 Write */
HAL_INI_WRITE_ARRAY(ah, ar5212Bank2_5111, modesIndex, regWrites);
/* Bank 3 Write */
HAL_INI_WRITE_ARRAY(ah, ar5212Bank3_5111, modesIndex, regWrites);
/* Bank 6 Write */
for (i = 0; i < NELEM(ar5212Bank6_5111); i++)
rfReg[i] = ar5212Bank6_5111[i][modesIndex];
if (IEEE80211_IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd84, 1, 51, 3);
ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd90, 1, 45, 3);
}
ar5212ModifyRfBuffer(rfReg, rfPwdXpd, 1, 95, 0);
ar5212ModifyRfBuffer(rfReg, rfXpdGainFixed, 4, 96, 0);
/* Set 5212 OB & DB */
ar5212ModifyRfBuffer(rfReg, tempOB, 3, 104, 0);
ar5212ModifyRfBuffer(rfReg, tempDB, 3, 107, 0);
HAL_INI_WRITE_BANK(ah, ar5212Bank6_5111, rfReg, regWrites);
/* Bank 7 Write */
for (i = 0; i < NELEM(ar5212Bank7_5111); i++)
rfReg[i] = ar5212Bank7_5111[i][modesIndex];
ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);
ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);
if (IEEE80211_IS_CHAN_QUARTER(chan) || IEEE80211_IS_CHAN_HALF(chan)) {
uint32_t rfWaitI, rfWaitS, rfMaxTime;
rfWaitS = 0x1f;
rfWaitI = (IEEE80211_IS_CHAN_HALF(chan)) ? 0x10 : 0x1f;
rfMaxTime = 3;
ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
}
HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites);
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar2316SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
{
#define RF_BANK_SETUP(_priv, _ix, _col) do { \
int i; \
for (i = 0; i < N(ar5212Bank##_ix##_2316); i++) \
(_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_2316[i][_col];\
} while (0)
struct ath_hal_5212 *ahp = AH5212(ah);
const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
uint16_t ob2GHz = 0, db2GHz = 0;
struct ar2316State *priv = AR2316(ah);
int regWrites = 0;
HALDEBUG(ah, HAL_DEBUG_RFPARAM,
"%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
__func__, chan->channel, chan->channelFlags, modesIndex);
HALASSERT(priv != AH_NULL);
/* Setup rf parameters */
switch (chan->channelFlags & CHANNEL_ALL) {
case CHANNEL_B:
ob2GHz = ee->ee_obFor24;
db2GHz = ee->ee_dbFor24;
break;
case CHANNEL_G:
case CHANNEL_108G:
ob2GHz = ee->ee_obFor24g;
db2GHz = ee->ee_dbFor24g;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
__func__, chan->channelFlags);
return AH_FALSE;
}
/* Bank 1 Write */
RF_BANK_SETUP(priv, 1, 1);
/* Bank 2 Write */
RF_BANK_SETUP(priv, 2, modesIndex);
/* Bank 3 Write */
RF_BANK_SETUP(priv, 3, modesIndex);
/* Bank 6 Write */
RF_BANK_SETUP(priv, 6, modesIndex);
ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 178, 0);
ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 175, 0);
/* Bank 7 Setup */
RF_BANK_SETUP(priv, 7, modesIndex);
/* Write Analog registers */
HAL_INI_WRITE_BANK(ah, ar5212Bank1_2316, priv->Bank1Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank2_2316, priv->Bank2Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank3_2316, priv->Bank3Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank6_2316, priv->Bank6Data, regWrites);
HAL_INI_WRITE_BANK(ah, ar5212Bank7_2316, priv->Bank7Data, regWrites);
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
#undef RF_BANK_SETUP
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
u_int16_t modesIndex, u_int16_t *rfXpdGain)
{
struct ath_hal_5212 *ahp = AH5212(ah);
u_int16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
u_int16_t tempOB, tempDB;
u_int32_t ob2GHz, db2GHz, rfReg[N(ar5212Bank6_5111)];
int i, regWrites = 0;
/* Setup rf parameters */
switch (chan->channelFlags & CHANNEL_ALL) {
case CHANNEL_A:
case CHANNEL_T:
if (4000 < chan->channel && chan->channel < 5260) {
tempOB = ahp->ah_ob1;
tempDB = ahp->ah_db1;
} else if (5260 <= chan->channel && chan->channel < 5500) {
tempOB = ahp->ah_ob2;
tempDB = ahp->ah_db2;
} else if (5500 <= chan->channel && chan->channel < 5725) {
tempOB = ahp->ah_ob3;
tempDB = ahp->ah_db3;
} else if (chan->channel >= 5725) {
tempOB = ahp->ah_ob4;
tempDB = ahp->ah_db4;
} else {
/* XXX when does this happen??? */
tempOB = tempDB = 0;
}
ob2GHz = db2GHz = 0;
rfXpdGainFixed = ahp->ah_xgain[headerInfo11A];
rfPloSel = ahp->ah_xpd[headerInfo11A];
rfPwdXpd = !ahp->ah_xpd[headerInfo11A];
gainI = ahp->ah_gainI[headerInfo11A];
break;
case CHANNEL_B:
tempOB = ahp->ah_obFor24;
tempDB = ahp->ah_dbFor24;
ob2GHz = ahp->ah_ob2GHz[0];
db2GHz = ahp->ah_db2GHz[0];
rfXpdGainFixed = ahp->ah_xgain[headerInfo11B];
rfPloSel = ahp->ah_xpd[headerInfo11B];
rfPwdXpd = !ahp->ah_xpd[headerInfo11B];
gainI = ahp->ah_gainI[headerInfo11B];
break;
case CHANNEL_G:
tempOB = ahp->ah_obFor24g;
tempDB = ahp->ah_dbFor24g;
ob2GHz = ahp->ah_ob2GHz[1];
db2GHz = ahp->ah_db2GHz[1];
rfXpdGainFixed = ahp->ah_xgain[headerInfo11G];
rfPloSel = ahp->ah_xpd[headerInfo11G];
rfPwdXpd = !ahp->ah_xpd[headerInfo11G];
gainI = ahp->ah_gainI[headerInfo11G];
break;
default:
HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid channel flags 0x%x\n",
__func__, chan->channelFlags);
return AH_FALSE;
}
HALASSERT(1 <= tempOB && tempOB <= 5);
HALASSERT(1 <= tempDB && tempDB <= 5);
/* Bank 0 Write */
for (i = 0; i < N(ar5212Bank0_5111); i++)
rfReg[i] = ar5212Bank0_5111[i][modesIndex];
if (IS_CHAN_2GHZ(chan)) {
ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
}
for (i = 0; i < N(ar5212Bank0_5111); i++) {
OS_REG_WRITE(ah, ar5212Bank0_5111[i][0], rfReg[i]);
ALLOW_DMA_READ_COMPLETE(regWrites);
}
/* Bank 1 Write */
REG_WRITE_ARRAY(ar5212Bank1_5111, 1, regWrites);
/* Bank 2 Write */
REG_WRITE_ARRAY(ar5212Bank2_5111, modesIndex, regWrites);
/* Bank 3 Write */
REG_WRITE_ARRAY(ar5212Bank3_5111, modesIndex, regWrites);
/* Bank 6 Write */
for (i = 0; i < N(ar5212Bank6_5111); i++)
rfReg[i] = ar5212Bank6_5111[i][modesIndex];
if (IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
ar5212ModifyRfBuffer(rfReg, ahp->ah_cornerCal.pd84, 1, 51, 3);
ar5212ModifyRfBuffer(rfReg, ahp->ah_cornerCal.pd90, 1, 45, 3);
}
ar5212ModifyRfBuffer(rfReg, rfPwdXpd, 1, 95, 0);
ar5212ModifyRfBuffer(rfReg, rfXpdGainFixed, 4, 96, 0);
/* Set 5212 OB & DB */
ar5212ModifyRfBuffer(rfReg, tempOB, 3, 104, 0);
ar5212ModifyRfBuffer(rfReg, tempDB, 3, 107, 0);
for (i = 0; i < N(ar5212Bank6_5111); i++) {
OS_REG_WRITE(ah, ar5212Bank6_5111[i][0], rfReg[i]);
ALLOW_DMA_READ_COMPLETE(regWrites);
}
/* Bank 7 Write */
for (i = 0; i < N(ar5212Bank7_5111); i++)
rfReg[i] = ar5212Bank7_5111[i][modesIndex];
ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);
ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);
if (IS_CHAN_QUARTER_RATE(chan) || IS_CHAN_HALF_RATE(chan)) {
u_int32_t rfWaitI, rfWaitS, rfMaxTime;
rfWaitS = 0x1f;
rfWaitI = (IS_CHAN_HALF_RATE(chan)) ? 0x10 : 0x1f;
rfMaxTime = 3;
ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
}
for (i = 0; i < N(ar5212Bank7_5111); i++) {
OS_REG_WRITE(ah, ar5212Bank7_5111[i][0], rfReg[i]);
ALLOW_DMA_READ_COMPLETE(regWrites);
}
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
}