void arm_cl2_config(vaddr_t pl310_base) { io_write32(pl310_base + PL310_CTRL, 0); l2_sram_config(RAMC_L2CC); io_write32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); io_write32(pl310_base + PL310_PREFETCH_CTRL, PL310_PREFETCH_CTRL_INIT); io_write32(pl310_base + PL310_POWER_CTRL, PL310_POWER_CTRL_INIT); /* invalidate all cache ways */ arm_cl2_invbyway(pl310_base); }
unsigned int cache_maintenance_l2(int op, paddr_t pa, size_t len) { unsigned int ret = TEE_SUCCESS; uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_IRQ); tee_l2cc_mutex_lock(); switch (op) { case L2CACHE_INVALIDATE: arm_cl2_invbyway(pl310_base()); break; case L2CACHE_AREA_INVALIDATE: if (len) arm_cl2_invbypa(pl310_base(), pa, pa + len - 1); break; case L2CACHE_CLEAN: arm_cl2_cleanbyway(pl310_base()); break; case L2CACHE_AREA_CLEAN: if (len) arm_cl2_cleanbypa(pl310_base(), pa, pa + len - 1); break; case L2CACHE_CLEAN_INV: arm_cl2_cleaninvbyway(pl310_base()); break; case L2CACHE_AREA_CLEAN_INV: if (len) arm_cl2_cleaninvbypa(pl310_base(), pa, pa + len - 1); break; default: ret = TEE_ERROR_NOT_IMPLEMENTED; } tee_l2cc_mutex_unlock(); thread_set_exceptions(exceptions); return ret; }