static uint32_t set_translation_table_entries(
const void *begin,
const void *end,
uint32_t section_flags
)
{
uint32_t cl_size = arm_cp15_get_min_cache_line_size();
uint32_t *ttb = arm_cp15_get_translation_table_base();
uint32_t i = ARM_MMU_SECT_GET_INDEX(begin);
uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end));
uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
uint32_t ctrl;
uint32_t section_flags_of_first_entry;
ctrl = arm_cp15_mmu_disable(cl_size);
arm_cp15_tlb_invalidate();
section_flags_of_first_entry = ttb [i];
while (i != iend) {
uint32_t addr = i << ARM_MMU_SECT_BASE_SHIFT;
ttb [i] = addr | section_flags;
i = (i + 1U) & index_mask;
}
arm_cp15_set_control(ctrl);
return section_flags_of_first_entry;
}
static void BSP_START_SECTION
lpc32xx_setup_translation_table_and_enable_mmu(uint32_t ctrl)
{
uint32_t const dac =
ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
size_t const config_entry_count =
sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
size_t i = 0;
arm_cp15_set_domain_access_control(dac);
arm_cp15_set_translation_table_base(ttb);
/* Initialize translation table with invalid entries */
for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
ttb [i] = 0;
}
for (i = 0; i < config_entry_count; ++i) {
lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
}
/* Enable MMU and cache */
ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
arm_cp15_set_control(ctrl);
}
void mmu_set_cpu_async_mode(void)
{
uint32_t reg;
reg = arm_cp15_get_control();
reg |= 0xc0000000;
arm_cp15_set_control(reg);
}
void rpi_start_rtems_on_secondary_processor(void)
{
uint32_t ctrl;
ctrl = arm_cp15_start_setup_mmu_and_cache(
0,
ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
);
rpi_ipi_initialize();
arm_cp15_set_domain_access_control(
ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
);
/* FIXME: Sharing the translation table between processors is brittle */
arm_cp15_set_translation_table_base(
(uint32_t *) bsp_translation_table_base
);
arm_cp15_tlb_invalidate();
ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
ctrl &= ~ARM_CP15_CTRL_V;
arm_cp15_set_control(ctrl);
_SMP_Start_multitasking_on_secondary_processor();
}
static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
{
uint32_t ctrl = 0;
/* Disable MMU and cache, basic settings */
ctrl = arm_cp15_get_control();
ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C
| ARM_CP15_CTRL_V | ARM_CP15_CTRL_M);
ctrl |= ARM_CP15_CTRL_S | ARM_CP15_CTRL_A;
arm_cp15_set_control(ctrl);
arm_cp15_cache_invalidate();
arm_cp15_tlb_invalidate();
#ifndef LPC32XX_DISABLE_MMU
lpc32xx_setup_translation_table_and_enable_mmu(ctrl);
#endif
}
void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
{
uint32_t sctlr_val;
sctlr_val = arm_cp15_get_control();
/*
* Current U-boot loader seems to start kernel image
* with I and D caches on and MMU enabled.
* If RTEMS application image finds that cache is on
* during startup then disable caches.
*/
if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
/*
* If the data cache is on then ensure that it is clean
* before switching off to be extra carefull.
*/
arm_cp15_drain_write_buffer();
arm_cp15_data_cache_clean_and_invalidate();
}
arm_cp15_flush_prefetch_buffer();
sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A);
arm_cp15_set_control(sctlr_val);
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();
arm_cp15_data_cache_invalidate();
arm_cp15_instruction_cache_invalidate();
}
/* Clear Translation Table Base Control Register */
arm_cp15_set_translation_table_base_control_register(0);
/* Clear Secure or Non-secure Vector Base Address Register */
arm_cp15_set_vector_base_address(0);
}
void mmu_init(mmu_sect_map_t *map)
{
mmu_lvl1_t *lvl1_base;
int i;
/* flush the cache and TLB */
arm_cp15_cache_invalidate();
arm_cp15_tlb_invalidate();
/* set manage mode access for all domains */
arm_cp15_set_domain_access_control(0xffffffff);
lvl1_base = (mmu_lvl1_t *)&_ttbl_base;
/* set up the trans table */
mmu_set_map_inval(lvl1_base);
arm_cp15_set_translation_table_base(lvl1_base);
/* create a 1:1 mapping of the entire address space */
i = 0;
while(map[i].size != 0) {
int c = 0; /* to avoid uninitialized warnings */
int b = 0; /* to avoid uninitialized warnings */
int pbase;
int vbase;
int sects;
switch (map[i].cache_flags) {
case MMU_CACHE_NONE:
c = 0;
b = 0;
break;
case MMU_CACHE_BUFFERED:
c = 0;
b = 1;
break;
case MMU_CACHE_WTHROUGH:
c = 1;
b = 0;
break;
case MMU_CACHE_WBACK:
c = 1;
b = 1;
break;
}
pbase = (map[i].paddr & 0xfff00000) >> 20;
vbase = (map[i].vaddr & 0xfff00000) >> 20;
sects = map[i].size;
while (sects > 0) {
lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
MMU_SECT_AP_ALL,
0,
c,
b);
pbase++;
vbase++;
sects--;
}
i++;
}
/* flush the cache and TLB */
arm_cp15_cache_invalidate();
arm_cp15_tlb_invalidate();
/* I & D caches turned on */
arm_cp15_set_control(MMU_CTRL_DEFAULT |
MMU_CTRL_D_CACHE_EN |
MMU_CTRL_I_CACHE_EN |
MMU_CTRL_ALIGN_FAULT_EN |
MMU_CTRL_LITTLE_ENDIAN |
MMU_CTRL_MMU_EN);
return;
}