void arm_cpu_boot(int cpu)
{
/* Enable SMP cache coherency for the CPU */
arm_enable_smp(cpu);
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
arm_gic_initialize();
#ifdef CONFIG_ARCH_LOWVECTORS
/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
* beginning of the .text region must appear at address at the address
* specified in the VBAR. There are two ways to accomplish this:
*
* 1. By explicitly mapping the beginning of .text region with a page
* table entry so that the virtual address zero maps to the beginning
* of the .text region. VBAR == 0x0000:0000.
*
* 2. Set the Cortex-A5 VBAR register so that the vector table address
* is moved to a location other than 0x0000:0000.
*
* The second method is used by this logic.
*/
/* Set the VBAR register to the address of the vector table */
DEBUGASSERT((((uintptr_t)&_vector_start) & ~VBAR_MASK) == 0);
cp15_wrvbar((uint32_t)&_vector_start);
#endif /* CONFIG_ARCH_LOWVECTORS */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
(void)up_irq_enable();
#endif
/* The next thing that we expect to happen is for logic running on CPU0
* to call up_cpu_start() which generate an SGI and a context switch to
* the configured NuttX IDLE task.
*/
for (; ; )
{
asm("WFI");
}
}
void up_boot(void)
{
#ifdef CONFIG_ARCH_RAMFUNCS
const uint32_t *src;
uint32_t *dest;
#endif
#ifndef CONFIG_ARCH_ROMPGTABLE
/* __start provided the basic MMU mappings for SRAM. Now provide mappings
* for all IO regions (Including the vector region).
*/
sam_setupmappings();
/* Provide a special mapping for the IRAM interrupt vector positioned in
* high memory.
*/
sam_vectormapping();
#endif /* CONFIG_ARCH_ROMPGTABLE */
#ifdef CONFIG_ARCH_RAMFUNCS
/* Copy any necessary code sections from FLASH to RAM. The correct
* destination in SRAM is given by _sramfuncs and _eramfuncs. The
* temporary location is in flash after the data initialization code
* at _framfuncs
*/
for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
{
*dest++ = *src++;
}
/* Flush the copied RAM functions into physical RAM so that will
* be available when fetched into the I-Cache.
*/
arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
#endif
/* Setup up vector block. _vector_start and _vector_end are exported from
* arm_vector.S
*/
sam_copyvectorblock();
/* Disable the watchdog timer */
sam_wdtdisable();
/* Initialize clocking to settings provided by board-specific logic */
sam_clockconfig();
#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
#endif
/* Perform board-specific initialization, This must include:
*
* - Initialization of board-specific memory resources (e.g., SDRAM)
* - Configuration of board specific resources (PIOs, LEDs, etc).
*
* NOTE: We must use caution prior to this point to make sure that
* the logic does not access any global variables that might lie
* in SDRAM.
*/
sam_boardinitialize();
#ifdef NEED_SDRAM_REMAPPING
/* SDRAM was configured in a temporary state to support low-level
* initialization. Now that the SDRAM has been fully initialized,
* we can reconfigure the SDRAM in its final, fully cache-able state.
*/
sam_remap();
#endif
#ifdef CONFIG_BOOT_SDRAM_DATA
/* If .data and .bss reside in SDRAM, then initialize the data sections
* now after SDRAM has been initialized.
*/
arm_data_initialize();
#endif
/* Perform common, low-level chip initialization (might do nothing) */
sam_lowsetup();
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization if we are going to use the serial
* driver.
*/
sam_earlyserialinit();
#endif
}
