/*
* Write value to the a PHY register
* Note: MDI interface is assumed to already have been enabled.
*/
static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
{
at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
| ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
/* Wait until IDLE bit in Network Status register is cleared */
at91_phy_wait();
}
static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
{
at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
| ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
at91_phy_wait();
}
static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
{
at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
| ((phy_addr & 0x1f) << 23) | (address << 18));
at91_phy_wait();
*value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
}
static int at91_ether_mii_write(struct mii_bus *dev, int addr, int reg, u16 val)
{
int ret;
enable_mdi();
at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
| ((addr & 0x1f) << 23) | (reg << 18) | (val & AT91_EMAC_DATA));
/* Wait until IDLE bit in Network Status register is cleared */
ret = at91_phy_wait();
disable_mdi();
return ret;
}
static int at91_ether_mii_read(struct mii_bus *dev, int addr, int reg)
{
int value;
enable_mdi();
at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
| ((addr & 0x1f) << 23) | (reg << 18));
/* Wait until IDLE bit in Network Status register is cleared */
value = at91_phy_wait();
if (value < 0)
goto out;
value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
out:
disable_mdi();
return value;
}
