void __init at91_add_device_nand(struct at91_nand_data *data)
{
	unsigned long csa, mode;

	if (!data)
		return;

	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
	at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
			| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));

	at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
			| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));

	at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));

	if (data->bus_width_16)
		mode = AT91_SMC_DBW_16;
	else
		mode = AT91_SMC_DBW_8;
	at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));

	/* enable pin */
	if (data->enable_pin)
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (data->rdy_pin)
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (data->det_pin)
		at91_set_gpio_input(data->det_pin, 1);

	nand_data = *data;
	platform_device_register(&at91sam9263_nand_device);
}
static void at91sam9261ek_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA,
		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
		       AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
		       AT91_SMC_DBW_8 |
#endif
		       AT91_SMC_TDF_(2));

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(AT91_PIN_PC15, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(AT91_PIN_PC14, 1);

	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
}
Пример #3
0
static void at91cap9_nor_hw_init(void)
{
    unsigned long csa;

    /* Ensure EBI supply is 3.3V */
    csa = at91_sys_read(AT91_MATRIX_EBICSA);
    at91_sys_write(AT91_MATRIX_EBICSA,
                   csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
    /* Configure SMC CS0 for parallel flash */
    at91_sys_write(AT91_SMC_SETUP(0),
                   AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
                   AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
    at91_sys_write(AT91_SMC_PULSE(0),
                   AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
                   AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
    at91_sys_write(AT91_SMC_CYCLE(0),
                   AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
    at91_sys_write(AT91_SMC_MODE(0),
                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
                   AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
                   AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
}
Пример #4
0
static __init void cap9adk_add_device_nor(void)
{
	unsigned long csa;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_SETUP(0), AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2)
			| AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));

	at91_sys_write(AT91_SMC_PULSE(0), AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10)
			| AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));

	at91_sys_write(AT91_SMC_CYCLE(0), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));

	at91_sys_write(AT91_SMC_MODE(0), AT91_SMC_READMODE | AT91_SMC_WRITEMODE
			| AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
			| AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));

	platform_device_register(&cap9adk_nor_flash);
}
Пример #5
0
static int at91sam9263_smc_init(void)
{
	unsigned long csa;

	if (!of_machine_is_compatible("atmel,at91sam9263ek"))
		return 0;

	/* setup bus-width (8 or 16) */
	if (IS_ENABLED(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16))
		ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
	else
		ek_nand_smc_config.mode |= AT91_SMC_DBW_8;

	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
	csa |= AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
	at91_sys_write(AT91_MATRIX_EBI0CSA, csa);

	/* configure chip-select 3 (NAND) */
	sam9_smc_configure(0, 3, &ek_nand_smc_config);

	return 0;
}
Пример #6
0
void __init at91_add_device_nand(struct at91_nand_data *data)
{
	unsigned long csa;

	if (!data)
		return;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
			| AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));

	at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
			| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));

	at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));

	at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));

	/* enable pin */
	if (data->enable_pin)
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (data->rdy_pin)
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (data->det_pin)
		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */

	nand_data = *data;
	platform_device_register(&at91_nand_device);
}
Пример #7
0
/*
 * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
 */
static void
pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* update clocksource counter */
		pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
		at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
				| AT91_PIT_PITIEN);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		BUG();
		/* FALLTHROUGH */
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		/* disable irq, leaving the clocksource active */
		at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
		break;
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}
Пример #8
0
/* we already mapped the I/O region */
static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
{
	struct at91_cf_socket	*cf;
	u32			csr;

	cf = container_of(s, struct at91_cf_socket, socket);
	io->flags &= (MAP_ACTIVE | MAP_16BIT | MAP_AUTOSZ);

	/*
	 * Use 16 bit accesses unless/until we need 8-bit i/o space.
	 * Always set CSR4 ... PCMCIA won't always unmap things.
	 */
	csr = at91_sys_read(AT91_SMC_CSR(4)) & ~AT91_SMC_DBW;

	/*
	 * NOTE: this CF controller ignores IOIS16, so we can't really do
	 * MAP_AUTOSZ.  The 16bit mode allows single byte access on either
	 * D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many
	 * purposes (and handles ide-cs).
	 *
	 * The 8bit mode is needed for odd byte access on D0-D7.  It seems
	 * some cards only like that way to get at the odd byte, despite
	 * CF 3.0 spec table 35 also giving the D8-D15 option.
	 */
	if (!(io->flags & (MAP_16BIT|MAP_AUTOSZ))) {
		csr |= AT91_SMC_DBW_8;
		pr_debug("%s: 8bit i/o bus\n", driver_name);
	} else {
		csr |= AT91_SMC_DBW_16;
		pr_debug("%s: 16bit i/o bus\n", driver_name);
	}
	at91_sys_write(AT91_SMC_CSR(4), csr);

	io->start = cf->socket.io_offset;
	io->stop = io->start + SZ_2K - 1;

	return 0;
}
Пример #9
0
int misc_init_r(void)
{
	char *str;
	char buf[32];

	/*
	 * Normally the processor clock has a divisor of 2.
	 * In some cases this this needs to be set to 4.
	 * Check the user has set environment mdiv to 4 to change the divisor.
	 */
	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
		at91_sys_write(AT91_PMC_MCKR,
			(at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
			AT91SAM9_PMC_MDIV_4);
		at91_clock_init(0);
		serial_setbrg();
		/* Notify the user that the clock is not default */
		printf("Setting master clock to %s MHz\n",
			strmhz(buf, get_mck_clk_rate()));
	}

	return 0;
}
Пример #10
0
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
	unsigned int csa;

	if (!data)
		return;

	/* enable the address range of CS3 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
		| AT91_SMC_NWS_(5)
		| AT91_SMC_TDF_(1)
		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

	/* enable pin */
	if (data->enable_pin)
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (data->rdy_pin)
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (data->det_pin)
		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */
	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */

	add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
			   IORESOURCE_MEM, data);
}
Пример #11
0
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
	unsigned int csa;

	if (!data)
		return;

	/* enable the address range of CS3 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
		| AT91_SMC_NWS_(5)
		| AT91_SMC_TDF_(1)
		| AT91_SMC_RWSETUP_(0)	/* tDS Data Set up Time 30 - ns */
		| AT91_SMC_RWHOLD_(1)	/* tDH Data Hold Time 20 - ns */
	);

	/* enable pin */
	if (gpio_is_valid(data->enable_pin))
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (gpio_is_valid(data->rdy_pin))
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (gpio_is_valid(data->det_pin))
		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */
	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */

	nand_data = *data;
	platform_device_register(&at91rm9200_nand_device);
}
Пример #12
0
static void at91_mute_pic(void)
{
	struct at91_gpio_chip *prev, *chip = NULL;
	unsigned long unmasked, muted;
	unsigned i;

	for (i = 0; i < gpio_banks; i++) {
		prev = chip;
		chip = &gpio_chip[i];
		if (!(*chip->nonroot_gpios))
			continue;

		unmasked = __raw_readl(chip->regbase + PIO_IMR);
		muted = unmasked & __ipipe_irqbits[i + 1];
		__raw_get_cpu_var(__ipipe_muted_irqs)
			[i + PIN_BASE / 32] = muted;
		__raw_writel(muted, chip->regbase + PIO_IDR);
	}

	unmasked = at91_sys_read(AT91_AIC_IMR);
	muted = unmasked & __ipipe_irqbits[0];
	__raw_get_cpu_var(__ipipe_muted_irqs)[0] = muted;
	at91_sys_write(AT91_AIC_IDCR, muted);
}
Пример #13
0
static void at91cap9_nand_hw_init(void)
{
    unsigned long csa;

    /* Enable CS3 */
    csa = at91_sys_read(AT91_MATRIX_EBICSA);
    at91_sys_write(AT91_MATRIX_EBICSA,
                   csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
                   AT91_MATRIX_EBI_VDDIOMSEL_3_3V);

    /* Configure SMC CS3 for NAND/SmartMedia */
    at91_sys_write(AT91_SMC_SETUP(3),
                   AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
                   AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
    at91_sys_write(AT91_SMC_PULSE(3),
                   AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
                   AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
    at91_sys_write(AT91_SMC_CYCLE(3),
                   AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
    at91_sys_write(AT91_SMC_MODE(3),
                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
                   AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
                   AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
                   AT91_SMC_DBW_8 |
#endif
                   AT91_SMC_TDF_(1));

    at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);

    /* RDY/BSY is not connected */

    /* Enable NandFlash */
    at91_set_gpio_output(AT91_PIN_PD15, 1);
}
Пример #14
0
static void at91sam9g20ek_macb_hw_init(void)
{
	unsigned long rstc;
	
	/* Enable clock */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA17) => PHY normal mode (not Test mode)
	 *	ERX0 (PA14) => PHY ADDR0
	 *	ERX1 (PA15) => PHY ADDR1
	 *	ERX2 (PA25) => PHY ADDR2
	 *	ERX3 (PA26) => PHY ADDR3
	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(pin_to_mask(AT91_PIN_PA14) |
	       pin_to_mask(AT91_PIN_PA15) |
	       pin_to_mask(AT91_PIN_PA17) |
	       pin_to_mask(AT91_PIN_PA25) |
	       pin_to_mask(AT91_PIN_PA26) |
	       pin_to_mask(AT91_PIN_PA28),
	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);

	rstc = at91_sys_read(AT91_RSTC_MR);

	/* Need to reset PHY -> 500ms reset */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
				     AT91_RSTC_URSTEN);

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);

	/* Wait for end hardware reset */
	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));

	/* Restore NRST value */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     (rstc) |
				     AT91_RSTC_URSTEN);

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PA14) |
	       pin_to_mask(AT91_PIN_PA15) |
	       pin_to_mask(AT91_PIN_PA17) |
	       pin_to_mask(AT91_PIN_PA25) |
	       pin_to_mask(AT91_PIN_PA26) |
	       pin_to_mask(AT91_PIN_PA28),
	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);

	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
#if defined(CONFIG_AT91SAM9G20EK)
	/*
	 * use PA10, PA11 for ETX2, ETX3.
	 * PA23 and PA24 are for TWI EEPROM
	 */
	at91_set_B_periph(AT91_PIN_PA10, 0);    /* ETX2 */
	at91_set_B_periph(AT91_PIN_PA11, 0);    /* ETX3 */
#else
	at91_set_B_periph(AT91_PIN_PA23, 0);    /* ETX2 */
	at91_set_B_periph(AT91_PIN_PA24, 0);    /* ETX3 */
#endif
	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
#endif

}
Пример #15
0
static rt_int32_t  at91_get_scl(void *data)
{
	return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
}
Пример #16
0
static void at91cap9_macb_hw_init(void)
{
    /* Enable clock */
    at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);

    /*
     * Disable pull-up on:
     *	RXDV (PB22) => PHY normal mode (not Test mode)
     *	ERX0 (PB25) => PHY ADDR0
     *	ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
     *
     * PHY has internal pull-down
     */
    writel(pin_to_mask(AT91_PIN_PB22) |
           pin_to_mask(AT91_PIN_PB25) |
           pin_to_mask(AT91_PIN_PB26),
           pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);

    /* Need to reset PHY -> 500ms reset */
    at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
                   (AT91_RSTC_ERSTL & (0x0D << 8)) |
                   AT91_RSTC_URSTEN);

    at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);

    /* Wait for end hardware reset */
    while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));

    /* Restore NRST value */
    at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
                   (AT91_RSTC_ERSTL & (0x0 << 8)) |
                   AT91_RSTC_URSTEN);

    /* Re-enable pull-up */
    writel(pin_to_mask(AT91_PIN_PB22) |
           pin_to_mask(AT91_PIN_PB25) |
           pin_to_mask(AT91_PIN_PB26),
           pin_to_controller(AT91_PIN_PA0) + PIO_PUER);

    at91_set_A_periph(AT91_PIN_PB21, 0);	/* ETXCK_EREFCK */
    at91_set_A_periph(AT91_PIN_PB22, 0);	/* ERXDV */
    at91_set_A_periph(AT91_PIN_PB25, 0);	/* ERX0 */
    at91_set_A_periph(AT91_PIN_PB26, 0);	/* ERX1 */
    at91_set_A_periph(AT91_PIN_PB27, 0);	/* ERXER */
    at91_set_A_periph(AT91_PIN_PB28, 0);	/* ETXEN */
    at91_set_A_periph(AT91_PIN_PB23, 0);	/* ETX0 */
    at91_set_A_periph(AT91_PIN_PB24, 0);	/* ETX1 */
    at91_set_A_periph(AT91_PIN_PB30, 0);	/* EMDIO */
    at91_set_A_periph(AT91_PIN_PB29, 0);	/* EMDC */

#ifndef CONFIG_RMII
    at91_set_B_periph(AT91_PIN_PC25, 0);	/* ECRS */
    at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
    at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
    at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
    at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
    at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
    at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
    at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
#endif
    /* Unlock EMAC, 3 0 2 1 sequence */
#define MP_MAC_KEY0	0x5969cb2a
#define MP_MAC_KEY1	0xb4a1872e
#define MP_MAC_KEY2	0x05683fbc
#define MP_MAC_KEY3	0x3634fba4
#define UNLOCK_MAC	0x00000008
    writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
    writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
    writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
    writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
    writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
}
Пример #17
0
static int at91_pm_enter(suspend_state_t state)
{
    u32 saved_lpr;
    at91_gpio_suspend();
    at91_irq_suspend();

    pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
             /* remember all the always-wake irqs */
             (at91_sys_read(AT91_PMC_PCSR)
              | (1 << AT91_ID_FIQ)
              | (1 << AT91_ID_SYS)
              | (at91_extern_irq))
             & at91_sys_read(AT91_AIC_IMR),
             state);

    switch (state) {
    /*
     * Suspend-to-RAM is like STANDBY plus slow clock mode, so
     * drivers must suspend more deeply:  only the master clock
     * controller may be using the main oscillator.
     */
    case PM_SUSPEND_MEM:
        /*
         * Ensure that clocks are in a valid state.
         */
        if (!at91_pm_verify_clocks())
            goto error;

        /*
         * Enter slow clock mode by switching over to clk32k and
         * turning off the main oscillator; reverse on wakeup.
         */
        if (slow_clock) {
#ifdef CONFIG_AT91_SLOW_CLOCK
            /* copy slow_clock handler to SRAM, and call it */
            memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
#endif
            slow_clock();
            break;
        } else {
            pr_info("AT91: PM - no slow clock mode enabled ...\n");
            /* FALLTHROUGH leaving master clock alone */
        }

    /*
     * STANDBY mode has *all* drivers suspended; ignores irqs not
     * marked as 'wakeup' event sources; and reduces DRAM power.
     * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
     * nothing fancy done with main or cpu clocks.
     */
    case PM_SUSPEND_STANDBY:
        /*
         * NOTE: the Wait-for-Interrupt instruction needs to be
         * in icache so no SDRAM accesses are needed until the
         * wakeup IRQ occurs and self-refresh is terminated.
         */
        asm("b 1f; .align 5; 1:");
        asm("mcr p15, 0, r0, c7, c10, 4");	/* drain write buffer */
        saved_lpr = sdram_selfrefresh_enable();
        asm("mcr p15, 0, r0, c7, c0, 4");	/* wait for interrupt */
        sdram_selfrefresh_disable(saved_lpr);
        break;

    case PM_SUSPEND_ON:
        asm("mcr p15, 0, r0, c7, c0, 4");	/* wait for interrupt */
        break;

    default:
        pr_debug("AT91: PM - bogus suspend state %d\n", state);
        goto error;
    }

    pr_debug("AT91: PM - wakeup %08x\n",
             at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));

error:
    target_state = PM_SUSPEND_ON;
    at91_irq_resume();
    at91_gpio_resume();
    return 0;
}
Пример #18
0
/**
 * This function will handle init uart
 */
void rt_hw_uart_init(void)
{
	rt_uint32_t  cd;
	#ifdef USE_UART1
	#define BAUDRATE  115200
	//rt_uint32_t	uart_rate;
	//at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB);
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
	writel(AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS, AT91SAM9260_BASE_US1 + AT91_US_CR);
	writel( AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | AT91_US_CHRL_8 | AT91_US_PAR_NONE | AT91_US_NBSTOP_1 | AT91_US_CHMODE_NORMAL, AT91SAM9260_BASE_US1 + AT91_US_MR);//0x100108c0
	//at91_sys_write(AT91_USART1 + AT91_US_MR, 0x000008c0);//0x100108c0
	cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE;
	writel(cd, AT91SAM9260_BASE_US1 + AT91_US_BRGR);
	writel(AT91_US_RXEN | AT91_US_TXEN, AT91SAM9260_BASE_US1 + AT91_US_CR);
	
	writel(0x1, AT91SAM9260_BASE_US1 + AT91_US_IER);
	/* install interrupt handler */
	rt_hw_interrupt_install(AT91SAM9260_ID_US1, rt_serial_handler, RT_NULL);
	rt_hw_interrupt_umask(AT91SAM9260_ID_US1);
	#endif
	#ifdef USE_UART3
	#define BAUDRATE  115200
	//rt_uint32_t	uart_rate;
	at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
	at91_sys_write(AT91_PIOB+0x04, (1<<10)|(1<<11));
	at91_sys_write(AT91_PIOB+0x70, (1<<10)|(1<<11));
	writel(AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS, AT91SAM9260_BASE_US1 + AT91_US_CR);
	writel( AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | AT91_US_CHRL_8 | AT91_US_PAR_NONE | AT91_US_NBSTOP_1 | AT91_US_CHMODE_NORMAL, AT91SAM9260_BASE_US3 + AT91_US_MR);
	cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE;
	writel(cd, AT91SAM9260_BASE_US3 + AT91_US_BRGR);
	writel(AT91_US_RXEN | AT91_US_TXEN, AT91SAM9260_BASE_US3 + AT91_US_CR);
	
	writel(0x1, AT91SAM9260_BASE_US3 + AT91_US_IER);
	/* install interrupt handler */
	rt_hw_interrupt_install(AT91SAM9260_ID_US3, rt_serial_handler, RT_NULL);
	rt_hw_interrupt_umask(AT91SAM9260_ID_US3);
	
	#endif
	#ifdef USE_DBGU
	#define BAUDRATE  115200
	//rt_uint32_t  cd;
	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
	//at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
	at91_sys_write(AT91_DBGU + AT91_US_CR, AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS);
	at91_sys_write(AT91_DBGU + AT91_US_IDR, 0xffffffff);
	at91_sys_write(AT91_DBGU + AT91_US_MR, AT91_US_USMODE_NORMAL | AT91_US_PAR_NONE);
	cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE;
	at91_sys_write(AT91_DBGU + AT91_US_BRGR, cd);
	at91_sys_write(AT91_DBGU + AT91_US_CR, AT91_US_RXEN | AT91_US_TXEN);
	
	at91_sys_read(AT91_DBGU + AT91_US_CSR); //read for clearing interrupt
	at91_sys_write(AT91_DBGU + AT91_US_IER, 0x1);
	#endif
}
Пример #19
0
void __naked __bare_init board_init_lowlevel(void)
{
	u32 r;
	int i;

	at91_sys_write(AT91_WDT_MR, CONFIG_SYS_WDTC_WDMR_VAL);

	/* configure PIOx as EBI0 D[16-31] */
#ifdef CONFIG_ARCH_AT91SAM9263
	__raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR);
	__raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR);
	__raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR);
#else
	__raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR);
	__raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR);
#endif

#if defined(AT91_MATRIX_EBI0CSA)
	at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL);
#else /* AT91_MATRIX_EBICSA */
	at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL);
#endif

	/* flash */
	at91_sys_write(AT91_SMC_MODE(0), CONFIG_SYS_SMC0_MODE0_VAL);

	at91_sys_write(AT91_SMC_CYCLE(0), CONFIG_SYS_SMC0_CYCLE0_VAL);

	at91_sys_write(AT91_SMC_PULSE(0), CONFIG_SYS_SMC0_PULSE0_VAL);

	at91_sys_write(AT91_SMC_SETUP(0), CONFIG_SYS_SMC0_SETUP0_VAL);

	/*
	 * PMC Check if the PLL is already initialized
	 */
	r = at91_sys_read(AT91_PMC_MCKR);
	if (r & AT91_PMC_CSS)
		goto end;

	/*
	 * Enable the Main Oscillator
	 */
	at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);

	do {
		r = at91_sys_read(AT91_PMC_SR);
	} while (!(r & AT91_PMC_MOSCS));

	/*
	 * PLLAR: x MHz for PCK
	 */
	at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);

	do {
		r = at91_sys_read(AT91_PMC_SR);
	} while (!(r & AT91_PMC_LOCKA));

	/*
	 * PCK/x = MCK Master Clock from SLOW
	 */
	at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);

	pmc_check_mckrdy();

	/*
	 * PCK/x = MCK Master Clock from PLLA
	 */
	at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);

	pmc_check_mckrdy();

	/*
	 * Init SDRAM
	 */

	/*
	 * SDRAMC Check if Refresh Timer Counter is already initialized
	 */
	r = at91_sys_read(AT91_SDRAMC_TR);
	if (r)
		goto end;

	/* SDRAMC_MR : Normal Mode */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);

	/* SDRAMC_TR - Refresh Timer register */
	at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1);

	/* SDRAMC_CR - Configuration register*/
	at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);

	/* Memory Device Type */
	at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL);

	/* SDRAMC_MR : Precharge All */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_MR : refresh */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);

	/* access SDRAM 8 times */
	for (i = 0; i < 8; i++)
		access_sdram();

	/* SDRAMC_MR : Load Mode Register */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_MR : Normal Mode */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_TR : Refresh Timer Counter */
	at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2);

	/* access SDRAM */
	access_sdram();

	/* User reset enable*/
	at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL);

#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
	/* MATRIX_MCFG - REMAP all masters */
	at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
#endif

end:
	board_init_lowlevel_return();
}
Пример #20
0
/*
 * initialize the som-9g20 for apcc.
 */
static void apcc_init(void)
{
    unsigned int cnt = 10000;

    { /* initialize PCK1 - this is output to the FPGA as clock reference.
       * select PLLA as clock source (18.432 * 42) and div by 32
       * 24.192 mHz.
       */
	at91_sys_write(AT91_PMC_PCKR(1), AT91_PMC_CSS_PLLA | AT91_PMC_PRES_32);

	/* Enable PCK1 output */
	at91_sys_write(AT91_PMC_SCER, AT91_PMC_PCK1);

	/* Wait for PCK1 to come ready or timeout */
	while (cnt-- > 0) {
	    volatile unsigned long scsr = at91_sys_read(AT91_PMC_SCSR);
	    if ((scsr & AT91_PMC_PCK1RDY) != 0) {
		break;
	    }
	}

	/* configure PB31 to be used as PCK1 */
	at91_set_A_periph(AT91_PIN_PB31, 0);
    }

    { /* initialize sensys fpga */

	/*
	 * Configure CS0 (Chip Select 0) for FPGA (SMC @ FFFFEC00)
	 *
	 * SETUP - 0x1F3F1F3F
	 * PULSE - 0x403F403F
	 * CYCLE - 0x013E013E
	 * MODE  - 0x000F0003
	 */
	at91_sys_write(AT91_SMC_SETUP(0),
		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(4) |
		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(4));

	at91_sys_write(AT91_SMC_PULSE(0),
		       AT91_SMC_NWEPULSE_(20) | AT91_SMC_NCS_WRPULSE_(20) |
		       AT91_SMC_NRDPULSE_(22) | AT91_SMC_NCS_RDPULSE_(22));

	at91_sys_write(AT91_SMC_CYCLE(0),
		       AT91_SMC_NWECYCLE_(35) | AT91_SMC_NRDCYCLE_(29));

	at91_sys_write(AT91_SMC_MODE(0),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(1));
    }

    {
	/* to conserve power, disable the AtoD of phy. 
	 */
        at91_set_gpio_output(AT91_PIN_PA22, 1);
    }

#ifdef CONFIG_HW_WATCHDOG
    {	/* set up watchdog port */
        at91_set_gpio_output(AT91_PIN_PB18, 1);
	WATCHDOG_RESET();
    }
#endif
}
Пример #21
0
void at91_irq_suspend(void)
{
	backups = at91_sys_read(AT91_AIC_IMR);
	at91_sys_write(AT91_AIC_IDCR, backups);
	at91_sys_write(AT91_AIC_IECR, wakeups);
}
Пример #22
0
static int __init at91_cf_probe(struct device *dev)
{
	struct at91_cf_socket	*cf;
	struct at91_cf_data	*board = dev->platform_data;
	struct platform_device	*pdev = to_platform_device(dev);
	struct resource		*io;
	unsigned int		csa;
	int			status;

	if (!board || !board->det_pin || !board->rst_pin)
		return -ENODEV;

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!io)
		return -ENODEV;

	cf = kcalloc(1, sizeof *cf, GFP_KERNEL);
	if (!cf)
		return -ENOMEM;

	cf->board = board;
	cf->pdev = pdev;
	dev_set_drvdata(dev, cf);

	/* CF takes over CS4, CS5, CS6 */
	csa = at91_sys_read(AT91_EBI_CSA);
	at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);

	/* force poweron defaults for these pins ... */
	(void) at91_set_A_periph(AT91_PIN_PC9, 0);	/* A25/CFRNW */
	(void) at91_set_A_periph(AT91_PIN_PC10, 0);	/* NCS4/CFCS */
	(void) at91_set_A_periph(AT91_PIN_PC11, 0);	/* NCS5/CFCE1 */
	(void) at91_set_A_periph(AT91_PIN_PC12, 0);	/* NCS6/CFCE2 */

	/* nWAIT is _not_ a default setting */
	(void) at91_set_A_periph(AT91_PIN_PC6, 1);	/*  nWAIT */

	/*
	 * Static memory controller timing adjustments.
	 * REVISIT:  these timings are in terms of MCK cycles, so
	 * when MCK changes (cpufreq etc) so must these values...
	 */
	at91_sys_write(AT91_SMC_CSR(4),
				  AT91_SMC_ACSS_STD
				| AT91_SMC_DBW_16
				| AT91_SMC_BAT
				| AT91_SMC_WSEN
				| AT91_SMC_NWS_(32)	/* wait states */
				| AT91_SMC_RWSETUP_(6)	/* setup time */
				| AT91_SMC_RWHOLD_(4)	/* hold time */
	);

	/* must be a GPIO; ergo must trigger on both edges */
	status = request_irq(board->det_pin, at91_cf_irq,
			SA_SAMPLE_RANDOM, driver_name, cf);
	if (status < 0)
		goto fail0;

	/*
	 * The card driver will request this irq later as needed.
	 * but it causes lots of "irqNN: nobody cared" messages
	 * unless we report that we handle everything (sigh).
	 * (Note:  DK board doesn't wire the IRQ pin...)
	 */
	if (board->irq_pin) {
		status = request_irq(board->irq_pin, at91_cf_irq,
				SA_SHIRQ, driver_name, cf);
		if (status < 0)
			goto fail0a;
		cf->socket.pci_irq = board->irq_pin;
	} else
		cf->socket.pci_irq = NR_IRQS + 1;

	/* pcmcia layer only remaps "real" memory not iospace */
	cf->socket.io_offset = (unsigned long) ioremap(CF_IO_PHYS, SZ_2K);
	if (!cf->socket.io_offset)
		goto fail1;

	/* reserve CS4, CS5, and CS6 regions; but use just CS4 */
	if (!request_mem_region(io->start, io->end + 1 - io->start,
				driver_name))
		goto fail1;

	pr_info("%s: irqs det #%d, io #%d\n", driver_name,
		board->det_pin, board->irq_pin);

	cf->socket.owner = THIS_MODULE;
	cf->socket.dev.dev = dev;
	cf->socket.ops = &at91_cf_ops;
	cf->socket.resource_ops = &pccard_static_ops;
	cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP
				| SS_CAP_MEM_ALIGN;
	cf->socket.map_size = SZ_2K;
	cf->socket.io[0].res = io;

	status = pcmcia_register_socket(&cf->socket);
	if (status < 0)
		goto fail2;

	return 0;

fail2:
	iounmap((void __iomem *) cf->socket.io_offset);
	release_mem_region(io->start, io->end + 1 - io->start);
fail1:
	if (board->irq_pin)
		free_irq(board->irq_pin, cf);
fail0a:
	free_irq(board->det_pin, cf);
fail0:
	at91_sys_write(AT91_EBI_CSA, csa);
	kfree(cf);
	return status;
}
static void at91sam9263ek_macb_hw_init(void)
{
	/* Enable clock */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PC25) => PHY normal mode (not Test mode)
	 * 	ERX0 (PE25) => PHY ADDR0
	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(pin_to_mask(AT91_PIN_PC25),
	       pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
	writel(pin_to_mask(AT91_PIN_PE25) |
	       pin_to_mask(AT91_PIN_PE26),
	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);

	/* Need to reset PHY -> 500ms reset */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
				     AT91_RSTC_URSTEN);

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);

	/* Wait for end hardware reset */
	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));

	/* Restore NRST value */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
				     AT91_RSTC_URSTEN);

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PC25),
	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
	writel(pin_to_mask(AT91_PIN_PE25) |
	       pin_to_mask(AT91_PIN_PE26),
	       pin_to_controller(AT91_PIN_PE0) + PIO_PUER);

	at91_set_A_periph(AT91_PIN_PE21, 0);	/* ETXCK_EREFCK */
	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ERXDV */
	at91_set_A_periph(AT91_PIN_PE25, 0);	/* ERX0 */
	at91_set_A_periph(AT91_PIN_PE26, 0);	/* ERX1 */
	at91_set_A_periph(AT91_PIN_PE27, 0);	/* ERXER */
	at91_set_A_periph(AT91_PIN_PE28, 0);	/* ETXEN */
	at91_set_A_periph(AT91_PIN_PE23, 0);	/* ETX0 */
	at91_set_A_periph(AT91_PIN_PE24, 0);	/* ETX1 */
	at91_set_A_periph(AT91_PIN_PE30, 0);	/* EMDIO */
	at91_set_A_periph(AT91_PIN_PE29, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_A_periph(AT91_PIN_PE22, 0);	/* ECRS */
	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
#endif

}
Пример #24
0
static unsigned long at91x40_gettimeoffset(void)
{
	return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
}
Пример #25
0
static int at91_pm_enter(suspend_state_t state)
{
	at91_gpio_suspend();
	at91_irq_suspend();

	pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
			/* remember all the always-wake irqs */
			(at91_sys_read(AT91_PMC_PCSR)
					| (1 << AT91_ID_FIQ)
					| (1 << AT91_ID_SYS)
					| (1 << AT91_ID_IRQ0)
					| (1 << AT91_ID_IRQ1)
					| (1 << AT91_ID_IRQ2)
					| (1 << AT91_ID_IRQ3)
					| (1 << AT91_ID_IRQ4)
					| (1 << AT91_ID_IRQ5)
					| (1 << AT91_ID_IRQ6))
				& at91_sys_read(AT91_AIC_IMR),
			state);

	switch (state) {
		/*
		 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
		 * drivers must suspend more deeply:  only the master clock
		 * controller may be using the main oscillator.
		 */
		case PM_SUSPEND_MEM:
			/*
			 * Ensure that clocks are in a valid state.
			 */
			if (!at91_pm_verify_clocks())
				goto error;

			/*
			 * Enter slow clock mode by switching over to clk32k and
			 * turning off the main oscillator; reverse on wakeup.
			 */
			if (slow_clock) {
				slow_clock();
				break;
			} else {
				/* DEVELOPMENT ONLY */
				pr_info("AT91: PM - no slow clock mode yet ...\n");
				/* FALLTHROUGH leaving master clock alone */
			}

		/*
		 * STANDBY mode has *all* drivers suspended; ignores irqs not
		 * marked as 'wakeup' event sources; and reduces DRAM power.
		 * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
		 * nothing fancy done with main or cpu clocks.
		 */
		case PM_SUSPEND_STANDBY:
			/*
			 * NOTE: the Wait-for-Interrupt instruction needs to be
			 * in icache so the SDRAM stays in self-refresh mode until
			 * the wakeup IRQ occurs.
			 */
			asm("b 1f; .align 5; 1:");
			asm("mcr p15, 0, r0, c7, c10, 4");	/* drain write buffer */
			at91_sys_write(AT91_SDRAMC_SRR, 1);	/* self-refresh mode */
			/* fall though to next state */

		case PM_SUSPEND_ON:
			asm("mcr p15, 0, r0, c7, c0, 4");	/* wait for interrupt */
			break;

		default:
			pr_debug("AT91: PM - bogus suspend state %d\n", state);
			goto error;
	}

	pr_debug("AT91: PM - wakeup %08x\n",
			at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));

error:
	target_state = PM_SUSPEND_ON;
	at91_irq_resume();
	at91_gpio_resume();
	return 0;
}
void __init at91_add_device_cf(struct at91_cf_data *data)
{
	struct platform_device *pdev;
	unsigned long csa;

	if (!data)
		return;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);

	switch (data->chipselect) {
	case 4:
		at91_set_multi_drive(AT91_PIN_PC8, 0);
		at91_set_A_periph(AT91_PIN_PC8, 0);
		csa |= AT91_MATRIX_CS4A_SMC_CF1;
		cf0_data = *data;
		pdev = &cf0_device;
		break;
	case 5:
		at91_set_multi_drive(AT91_PIN_PC9, 0);
		at91_set_A_periph(AT91_PIN_PC9, 0);
		csa |= AT91_MATRIX_CS5A_SMC_CF2;
		cf1_data = *data;
		pdev = &cf1_device;
		break;
	default:
		printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
		       data->chipselect);
		return;
	}

	at91_sys_write(AT91_MATRIX_EBICSA, csa);

	if (data->rst_pin) {
		at91_set_multi_drive(data->rst_pin, 0);
		at91_set_gpio_output(data->rst_pin, 1);
	}

	if (data->irq_pin) {
		at91_set_gpio_input(data->irq_pin, 0);
		at91_set_deglitch(data->irq_pin, 1);
	}

	if (data->det_pin) {
		at91_set_gpio_input(data->det_pin, 0);
		at91_set_deglitch(data->det_pin, 1);
	}

	at91_set_B_periph(AT91_PIN_PC6, 0);     /* CFCE1 */
	at91_set_B_periph(AT91_PIN_PC7, 0);     /* CFCE2 */
	at91_set_A_periph(AT91_PIN_PC10, 0);    /* CFRNW */
	at91_set_A_periph(AT91_PIN_PC15, 1);    /* NWAIT */

	if (data->flags & AT91_CF_TRUE_IDE)
#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
		pdev->name = "pata_at91";
#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
		pdev->name = "at91_ide";
#else
#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
#endif
	else
Пример #27
0
static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
{
	at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
	timer_tick();
	return IRQ_HANDLED;
}