static int
ata_ati_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
/* IXP600 & IXP700 only have 1 PATA channel */
if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
(ctlr->chip->chipid == ATA_ATI_IXP700))
ctlr->channels = 1;
/* The SB600 needs special treatment. */
if (ctlr->chip->cfg1 & ATI_AHCI) {
/* Check if the chip is configured as an AHCI part. */
if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
(pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) {
ctlr->setmode = ata_sata_setmode;
if (ata_ahci_chipinit(dev) != ENXIO)
return 0;
}
}
ctlr->setmode = ata_ati_setmode;
return 0;
}
static int
ata_jmicron_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
device_t child;
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
/* do we have multiple PCI functions ? */
if (pci_read_config(dev, 0xdf, 1) & 0x40) {
/* are we on the AHCI part ? */
if (ata_ahci_chipinit(dev) != ENXIO)
return 0;
/* otherwise we are on the PATA part */
ctlr->ch_attach = ata_jmicron_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_generic_reset;
ctlr->setmode = ata_jmicron_setmode;
ctlr->channels = ctlr->chip->cfg2;
}
else {
/* set controller configuration to a combined setup we support */
pci_write_config(dev, 0x40, 0x80c0a131, 4);
pci_write_config(dev, 0x80, 0x01200000, 4);
/* Create AHCI subdevice if AHCI part present. */
if (ctlr->chip->cfg1) {
child = device_add_child(dev, NULL, -1);
if (child != NULL) {
device_set_ivars(child, (void *)(intptr_t)-1);
bus_generic_attach(dev);
}
}
ctlr->ch_attach = ata_jmicron_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_generic_reset;
ctlr->setmode = ata_jmicron_setmode;
ctlr->channels = ctlr->chip->cfg2;
}
return 0;
}
static int
ata_ali_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
struct ali_sata_resources *res;
int i, rid;
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
switch (ctlr->chip->cfg2) {
case ALI_SATA:
ctlr->channels = ctlr->chip->cfg1;
ctlr->ch_attach = ata_ali_sata_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
/* AHCI mode is correctly supported only on the ALi 5288. */
if ((ctlr->chip->chipid == ATA_ALI_5288) &&
(ata_ahci_chipinit(dev) != ENXIO))
return 0;
/* Allocate resources for later use by channel attach routines. */
res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
for (i = 0; i < 4; i++) {
rid = PCIR_BAR(i);
res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
RF_ACTIVE);
if (res->bars[i] == NULL) {
device_printf(dev, "Failed to allocate BAR %d\n", i);
for (i--; i >=0; i--)
bus_release_resource(dev, SYS_RES_IOPORT,
PCIR_BAR(i), res->bars[i]);
free(res, M_TEMP);
return ENXIO;
}
}
ctlr->chipset_data = res;
break;
case ALI_NEW:
/* use device interrupt as byte count end */
pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
/* enable cable detection and UDMA support on revisions < 0xc7 */
if (ctlr->chip->chiprev < 0xc7)
pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
0x09, 1);
/* enable ATAPI UDMA mode (even if we are going to do PIO) */
pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
(ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
/* only chips with revision > 0xc4 can do 48bit DMA */
if (ctlr->chip->chiprev <= 0xc4)
device_printf(dev,
"using PIO transfers above 137GB as workaround for "
"48bit DMA access bug, expect reduced performance\n");
ctlr->ch_attach = ata_ali_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_ali_reset;
ctlr->setmode = ata_ali_setmode;
break;
case ALI_OLD:
/* deactivate the ATAPI FIFO and enable ATAPI UDMA */
pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
ctlr->setmode = ata_ali_setmode;
break;
}
return 0;
}
static int
ata_via_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
/* AHCI SATA */
if (ctlr->chip->cfg2 & VIAAHCI) {
if (ata_ahci_chipinit(dev) != ENXIO)
return (0);
}
/* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
if (ctlr->chip->cfg2 & VIASATA) {
ctlr->ch_attach = ata_via_sata_ch_attach;
ctlr->setmode = ata_via_sata_setmode;
ctlr->getrev = ata_via_sata_getrev;
ctlr->reset = ata_via_sata_reset;
return 0;
}
/* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */
if (ctlr->chip->max_dma >= ATA_SA150) {
ctlr->r_type2 = SYS_RES_IOPORT;
ctlr->r_rid2 = PCIR_BAR(5);
if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))) {
ctlr->ch_attach = ata_via_ch_attach;
ctlr->ch_detach = ata_via_ch_detach;
ctlr->reset = ata_via_reset;
}
if (ctlr->chip->cfg2 & VIABAR) {
ctlr->channels = 3;
ctlr->setmode = ata_via_new_setmode;
} else
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
return 0;
}
/* prepare for ATA-66 on the 82C686a and 82C596b */
if (ctlr->chip->cfg2 & VIACLK)
pci_write_config(dev, 0x50, 0x030b030b, 4);
/* the southbridge might need the data corruption fix */
if (ctlr->chip->cfg2 & VIABUG)
ata_via_southbridge_fixup(dev);
/* set fifo configuration half'n'half */
pci_write_config(dev, 0x43,
(pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
/* set status register read retry */
pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
/* set DMA read & end-of-sector fifo flush */
pci_write_config(dev, 0x46,
(pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
/* set sector size */
pci_write_config(dev, 0x60, DEV_BSIZE, 2);
pci_write_config(dev, 0x68, DEV_BSIZE, 2);
ctlr->setmode = ata_via_old_setmode;
return 0;
}
