static void ath_fill_led_pin(struct ath_softc *sc) { struct ath_hw *ah = sc->sc_ah; /* Set default led pin if invalid */ if (ah->led_pin < 0) { if (AR_SREV_9287(ah)) ah->led_pin = ATH_LED_PIN_9287; else if (AR_SREV_9485(ah)) ah->led_pin = ATH_LED_PIN_9485; else if (AR_SREV_9300(ah)) ah->led_pin = ATH_LED_PIN_9300; else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) ah->led_pin = ATH_LED_PIN_9462; else ah->led_pin = ATH_LED_PIN_DEF; } /* Configure gpio for output */ ath9k_hw_gpio_request_out(ah, ah->led_pin, "ath9k-led", AR_GPIO_OUTPUT_MUX_AS_OUTPUT); /* LED off, active low */ ath9k_hw_set_gpio(ah, ah->led_pin, ah->config.led_active_high ? 0 : 1); }
static void ar9003_mci_observation_set_up(struct ath_hw *ah) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) { ath9k_hw_gpio_request_out(ah, 3, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA); ath9k_hw_gpio_request_out(ah, 2, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK); ath9k_hw_gpio_request_out(ah, 1, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); ath9k_hw_gpio_request_out(ah, 0, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) { ath9k_hw_gpio_request_out(ah, 3, NULL, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX); ath9k_hw_gpio_request_out(ah, 2, NULL, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX); ath9k_hw_gpio_request_out(ah, 1, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX); ath9k_hw_gpio_request_out(ah, 0, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX); ath9k_hw_gpio_request_out(ah, 5, NULL, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) { ath9k_hw_gpio_request_out(ah, 3, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX); ath9k_hw_gpio_request_out(ah, 2, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX); ath9k_hw_gpio_request_out(ah, 1, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); ath9k_hw_gpio_request_out(ah, 0, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); } else return; REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1); REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0); REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1); REG_WRITE(ah, AR_OBS, 0x4b); REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03); REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01); REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02); REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03); REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07); }