bool
ICBinaryArith_Int32::Compiler::generateStubCode(MacroAssembler &masm)
{
// Guard that R0 is an integer and R1 is an integer.
Label failure;
masm.branchTestInt32(Assembler::NotEqual, R0, &failure);
masm.branchTestInt32(Assembler::NotEqual, R1, &failure);
// Add R0 and R1. Don't need to explicitly unbox, just use R2's payloadReg.
Register scratchReg = R2.payloadReg();
// DIV and MOD need an extra non-volatile ValueOperand to hold R0.
GeneralRegisterSet savedRegs = availableGeneralRegs(2);
savedRegs = GeneralRegisterSet::Intersect(GeneralRegisterSet::NonVolatile(), savedRegs);
ValueOperand savedValue = savedRegs.takeAnyValue();
Label goodMul, divTest1, divTest2;
switch(op_) {
case JSOP_ADD:
// We know R0.typeReg() already contains the integer tag. No boxing
// required.
masm.ma_addTestOverflow(R0.payloadReg(), R0.payloadReg(), R1.payloadReg(), &failure);
break;
case JSOP_SUB:
masm.ma_subTestOverflow(R0.payloadReg(), R0.payloadReg(), R1.payloadReg(), &failure);
break;
case JSOP_MUL: {
masm.ma_mul_branch_overflow(scratchReg, R0.payloadReg(), R1.payloadReg(), &failure);
masm.ma_b(scratchReg, Imm32(0), &goodMul, Assembler::NotEqual, ShortJump);
// Result is -0 if operands have different signs.
masm.as_xor(t8, R0.payloadReg(), R1.payloadReg());
masm.ma_b(t8, Imm32(0), &failure, Assembler::LessThan, ShortJump);
masm.bind(&goodMul);
masm.move32(scratchReg, R0.payloadReg());
break;
}
case JSOP_DIV:
case JSOP_MOD: {
// Check for INT_MIN / -1, it results in a double.
masm.ma_b(R0.payloadReg(), Imm32(INT_MIN), &divTest1, Assembler::NotEqual, ShortJump);
masm.ma_b(R1.payloadReg(), Imm32(-1), &failure, Assembler::Equal, ShortJump);
masm.bind(&divTest1);
// Check for division by zero
masm.ma_b(R1.payloadReg(), Imm32(0), &failure, Assembler::Equal, ShortJump);
// Check for 0 / X with X < 0 (results in -0).
masm.ma_b(R0.payloadReg(), Imm32(0), &divTest2, Assembler::NotEqual, ShortJump);
masm.ma_b(R1.payloadReg(), Imm32(0), &failure, Assembler::LessThan, ShortJump);
masm.bind(&divTest2);
masm.as_div(R0.payloadReg(), R1.payloadReg());
if (op_ == JSOP_DIV) {
// Result is a double if the remainder != 0.
masm.as_mfhi(scratchReg);
masm.ma_b(scratchReg, Imm32(0), &failure, Assembler::NotEqual, ShortJump);
masm.as_mflo(scratchReg);
masm.tagValue(JSVAL_TYPE_INT32, scratchReg, R0);
} else {
Label done;
// If X % Y == 0 and X < 0, the result is -0.
masm.as_mfhi(scratchReg);
masm.ma_b(scratchReg, Imm32(0), &done, Assembler::NotEqual, ShortJump);
masm.ma_b(R0.payloadReg(), Imm32(0), &failure, Assembler::LessThan, ShortJump);
masm.bind(&done);
masm.tagValue(JSVAL_TYPE_INT32, scratchReg, R0);
}
break;
}
case JSOP_BITOR:
masm.ma_or(R0.payloadReg() , R0.payloadReg(), R1.payloadReg());
break;
case JSOP_BITXOR:
masm.ma_xor(R0.payloadReg() , R0.payloadReg(), R1.payloadReg());
break;
case JSOP_BITAND:
masm.ma_and(R0.payloadReg() , R0.payloadReg(), R1.payloadReg());
break;
case JSOP_LSH:
// MIPS will only use 5 lowest bits in R1 as shift offset.
masm.ma_sll(R0.payloadReg(), R0.payloadReg(), R1.payloadReg());
break;
case JSOP_RSH:
masm.ma_sra(R0.payloadReg(), R0.payloadReg(), R1.payloadReg());
break;
case JSOP_URSH:
masm.ma_srl(scratchReg, R0.payloadReg(), R1.payloadReg());
if (allowDouble_) {
Label toUint;
masm.ma_b(scratchReg, Imm32(0), &toUint, Assembler::LessThan, ShortJump);
// Move result and box for return.
masm.move32(scratchReg, R0.payloadReg());
EmitReturnFromIC(masm);
masm.bind(&toUint);
masm.convertUInt32ToDouble(scratchReg, FloatReg1);
masm.boxDouble(FloatReg1, R0);
} else {
masm.ma_b(scratchReg, Imm32(0), &failure, Assembler::LessThan, ShortJump);
// Move result for return.
masm.move32(scratchReg, R0.payloadReg());
}
break;
default:
MOZ_ASSUME_UNREACHABLE("Unhandled op for BinaryArith_Int32.");
}
EmitReturnFromIC(masm);
// Failure case - jump to next stub
masm.bind(&failure);
EmitStubGuardFailure(masm);
return true;
}
bool
ICBinaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
{
// Guard that R0 is an integer and R1 is an integer.
Label failure;
masm.branchTestInt32(Assembler::NotEqual, R0, &failure);
masm.branchTestInt32(Assembler::NotEqual, R1, &failure);
// Add R0 and R1. Don't need to explicitly unbox, just use R2.
Register Rscratch = R2_;
ARMRegister Wscratch = ARMRegister(Rscratch, 32);
#ifdef MERGE
// DIV and MOD need an extra non-volatile ValueOperand to hold R0.
AllocatableGeneralRegisterSet savedRegs(availableGeneralRegs(2));
savedRegs.set() = GeneralRegisterSet::Intersect(GeneralRegisterSet::NonVolatile(), savedRegs);
#endif
// get some more ARM-y names for the registers
ARMRegister W0(R0_, 32);
ARMRegister X0(R0_, 64);
ARMRegister W1(R1_, 32);
ARMRegister X1(R1_, 64);
ARMRegister WTemp(ExtractTemp0, 32);
ARMRegister XTemp(ExtractTemp0, 64);
Label maybeNegZero, revertRegister;
switch(op_) {
case JSOP_ADD:
masm.Adds(WTemp, W0, Operand(W1));
// Just jump to failure on overflow. R0 and R1 are preserved, so we can
// just jump to the next stub.
masm.j(Assembler::Overflow, &failure);
// Box the result and return. We know R0 already contains the
// integer tag, so we just need to move the payload into place.
masm.movePayload(ExtractTemp0, R0_);
break;
case JSOP_SUB:
masm.Subs(WTemp, W0, Operand(W1));
masm.j(Assembler::Overflow, &failure);
masm.movePayload(ExtractTemp0, R0_);
break;
case JSOP_MUL:
masm.mul32(R0.valueReg(), R1.valueReg(), Rscratch, &failure, &maybeNegZero);
masm.movePayload(Rscratch, R0_);
break;
case JSOP_DIV:
case JSOP_MOD: {
// Check for INT_MIN / -1, it results in a double.
Label check2;
masm.Cmp(W0, Operand(INT_MIN));
masm.B(&check2, Assembler::NotEqual);
masm.Cmp(W1, Operand(-1));
masm.j(Assembler::Equal, &failure);
masm.bind(&check2);
Label no_fail;
// Check for both division by zero and 0 / X with X < 0 (results in -0).
masm.Cmp(W1, Operand(0));
// If x > 0, then it can't be bad.
masm.B(&no_fail, Assembler::GreaterThan);
// if x == 0, then ignore any comparison, and force
// it to fail, if x < 0 (the only other case)
// then do the comparison, and fail if y == 0
masm.Ccmp(W0, Operand(0), vixl::ZFlag, Assembler::NotEqual);
masm.B(&failure, Assembler::Equal);
masm.bind(&no_fail);
masm.Sdiv(Wscratch, W0, W1);
// Start calculating the remainder, x - (x / y) * y.
masm.mul(WTemp, W1, Wscratch);
if (op_ == JSOP_DIV) {
// Result is a double if the remainder != 0, which happens
// when (x/y)*y != x.
masm.branch32(Assembler::NotEqual, R0.valueReg(), ExtractTemp0, &revertRegister);
masm.movePayload(Rscratch, R0_);
} else {
// Calculate the actual mod. Set the condition code, so we can see if it is non-zero.
masm.Subs(WTemp, W0, WTemp);
// If X % Y == 0 and X < 0, the result is -0.
masm.Ccmp(W0, Operand(0), vixl::NoFlag, Assembler::Equal);
masm.branch(Assembler::LessThan, &revertRegister);
masm.movePayload(ExtractTemp0, R0_);
}
break;
}
// ORR, EOR, AND can trivially be coerced int
// working without affecting the tag of the dest..
case JSOP_BITOR:
masm.Orr(X0, X0, Operand(X1));
break;
case JSOP_BITXOR:
masm.Eor(X0, X0, Operand(W1, vixl::UXTW));
break;
case JSOP_BITAND:
masm.And(X0, X0, Operand(X1));
break;
// LSH, RSH and URSH can not.
case JSOP_LSH:
// ARM will happily try to shift by more than 0x1f.
masm.Lsl(Wscratch, W0, W1);
masm.movePayload(Rscratch, R0.valueReg());
break;
case JSOP_RSH:
masm.Asr(Wscratch, W0, W1);
masm.movePayload(Rscratch, R0.valueReg());
break;
case JSOP_URSH:
masm.Lsr(Wscratch, W0, W1);
if (allowDouble_) {
Label toUint;
// Testing for negative is equivalent to testing bit 31
masm.Tbnz(Wscratch, 31, &toUint);
// Move result and box for return.
masm.movePayload(Rscratch, R0_);
EmitReturnFromIC(masm);
masm.bind(&toUint);
masm.convertUInt32ToDouble(Rscratch, ScratchDoubleReg);
masm.boxDouble(ScratchDoubleReg, R0, ScratchDoubleReg);
} else {
// Testing for negative is equivalent to testing bit 31
masm.Tbnz(Wscratch, 31, &failure);
// Move result for return.
masm.movePayload(Rscratch, R0_);
}
break;
default:
MOZ_CRASH("Unhandled op for BinaryArith_Int32.");
}
EmitReturnFromIC(masm);
switch (op_) {
case JSOP_MUL:
masm.bind(&maybeNegZero);
// Result is -0 if exactly one of lhs or rhs is negative.
masm.Cmn(W0, W1);
masm.j(Assembler::Signed, &failure);
// Result is +0, so use the zero register.
masm.movePayload(rzr, R0_);
EmitReturnFromIC(masm);
break;
case JSOP_DIV:
case JSOP_MOD:
masm.bind(&revertRegister);
break;
default:
break;
}
// Failure case - jump to next stub.
masm.bind(&failure);
EmitStubGuardFailure(masm);
return true;
}