static void b43_radio_2059_init_pre(struct b43_wldev *dev) { b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU); b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_FORCE); b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_FORCE); b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_CHIP0_PU); }
/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev, bool blocked) { if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) b43err(dev->wl, "MAC not suspended\n"); /* In the following PHY ops we copy wl's dummy behaviour. * TODO: Find out if reads (currently hidden in masks/masksets) are * needed and replace following ops with just writes or w&r. * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can * cause delayed (!) machine lock up. */ if (blocked) { b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0); } else { b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0); b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1); b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0); b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2); if (dev->phy.radio_ver == 0x2059) b43_radio_2059_init(dev); else B43_WARN_ON(1); b43_switch_channel(dev, dev->phy.channel); } }
void b43_phy_inita(struct b43_wldev *dev) { struct ssb_bus *bus = dev->dev->bus; struct b43_phy *phy = &dev->phy; /* This lowlevel A-PHY init is also called from G-PHY init. * So we must not access phy->a, if called from G-PHY code. */ B43_WARN_ON((phy->type != B43_PHYTYPE_A) && (phy->type != B43_PHYTYPE_G)); might_sleep(); if (phy->rev >= 6) { if (phy->type == B43_PHYTYPE_A) b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000); if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) b43_phy_set(dev, B43_PHY_ENCORE, 0x0010); else b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010); } b43_wa_all(dev); if (phy->type == B43_PHYTYPE_A) { if (phy->gmode && (phy->rev < 3)) b43_phy_set(dev, 0x0034, 0x0001); b43_phy_rssiagc(dev, 0); b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); b43_radio_init2060(dev); if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) && ((bus->boardinfo.type == SSB_BOARD_BU4306) || (bus->boardinfo.type == SSB_BOARD_BU4309))) { ; //TODO: A PHY LO } if (phy->rev >= 3) b43_phy_ww(dev); hardware_pctl_init_aphy(dev); //TODO: radar detection } if ((phy->type == B43_PHYTYPE_G) && (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) { b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); } }
static void b43_phy_ht_spur_avoid(struct b43_wldev *dev, struct ieee80211_channel *new_channel) { struct bcma_device *core = dev->dev->bdev; int spuravoid = 0; /* Check for 13 and 14 is just a guess, we don't have enough logs. */ if (new_channel->hw_value == 13 || new_channel->hw_value == 14) spuravoid = 1; bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false); bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid); bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_80211_PLL_REQ | B43_BCMA_CLKCTLST_PHY_PLL_REQ, B43_BCMA_CLKCTLST_80211_PLL_ST | B43_BCMA_CLKCTLST_PHY_PLL_ST, false); b43_mac_switch_freq(dev, spuravoid); b43_wireless_core_phy_pll_reset(dev); if (spuravoid) b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX); else b43_phy_mask(dev, B43_PHY_HT_BBCFG, ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF); b43_phy_ht_reset_cca(dev); }
static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev) { struct b43_phy_ht *phy_ht = dev->phy.ht; static const u16 base[] = { 0x840, 0x860, 0x880 }; u16 save_regs[3][3]; s32 rssi_buf[6]; int core; for (core = 0; core < 3; core++) { save_regs[core][1] = b43_phy_read(dev, base[core] + 6); save_regs[core][2] = b43_phy_read(dev, base[core] + 7); save_regs[core][0] = b43_phy_read(dev, base[core] + 0); b43_phy_write(dev, base[core] + 6, 0); b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */ b43_phy_set(dev, base[core] + 0, 0x0400); b43_phy_set(dev, base[core] + 0, 0x1000); } b43_phy_ht_tx_tone(dev); udelay(20); b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1); b43_phy_ht_stop_playback(dev); b43_phy_ht_reset_cca(dev); phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff; phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff; phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff; for (core = 0; core < 3; core++) { b43_phy_write(dev, base[core] + 0, save_regs[core][0]); b43_phy_write(dev, base[core] + 6, save_regs[core][1]); b43_phy_write(dev, base[core] + 7, save_regs[core][2]); } }
static void b43_wa_boards_g(struct b43_wldev *dev) { struct ssb_sprom *sprom = dev->dev->bus_sprom; struct b43_phy *phy = &dev->phy; if (dev->dev->board_vendor != SSB_BOARDVENDOR_BCM || dev->dev->board_type != SSB_BOARD_BU4306 || dev->dev->board_rev != 0x17) { if (phy->rev < 2) { b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001); } else { b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001); if ((sprom->boardflags_lo & B43_BFL_EXTLNA) && (phy->rev >= 7)) { b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000); b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002); } } } if (sprom->boardflags_lo & B43_BFL_FEM) { b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120); b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480); } }
/* Tune the hardware to a new channel. */ static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel) { const struct b43_nphy_channeltab_entry *tabent; tabent = b43_nphy_get_chantabent(dev, channel); if (!tabent) return -ESRCH; //FIXME enable/disable band select upper20 in RXCTL if (0 /*FIXME 5Ghz*/) b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20); else b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50); b43_chantab_radio_upload(dev, tabent); udelay(50); b43_radio_write16(dev, B2055_VCO_CAL10, 5); b43_radio_write16(dev, B2055_VCO_CAL10, 45); b43_radio_write16(dev, B2055_VCO_CAL10, 65); udelay(300); if (0 /*FIXME 5Ghz*/) b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); else b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); b43_chantab_phy_upload(dev, tabent); b43_nphy_tx_power_fix(dev); return 0; }
static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on) { if (on) { b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7); } else { b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7); b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7); } }
static void b43_phy_ht_channel_setup(struct b43_wldev *dev, const struct b43_phy_ht_channeltab_e_phy *e, struct ieee80211_channel *new_channel) { if (new_channel->band == NL80211_BAND_5GHZ) { /* Switch to 2 GHz for a moment to access B-PHY regs */ b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ); b43_phy_ht_bphy_reset(dev, true); /* Switch to 5 GHz */ b43_phy_set(dev, B43_PHY_HT_BANDCTL, B43_PHY_HT_BANDCTL_5GHZ); } else { /* Switch to 2 GHz */ b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ); b43_phy_ht_bphy_reset(dev, false); } b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1); b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2); b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3); b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4); b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5); b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6); if (new_channel->hw_value == 14) { b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0); b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800); } else { b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, B43_PHY_HT_CLASS_CTL_OFDM_EN); if (new_channel->band == NL80211_BAND_2GHZ) b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840); } if (1) /* TODO: On N it's for early devices only, what about HT? */ b43_phy_ht_tx_power_fix(dev); b43_phy_ht_spur_avoid(dev, new_channel); b43_phy_write(dev, 0x017e, 0x3830); }
static void b43_radio_init2055_pre(struct b43_wldev *dev) { b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_PORFORCE); b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU | B43_NPHY_RFCTL_CMD_OEPORFORCE); b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_PORFORCE); }
/* wlc_phy_init_lcnphy */ static int b43_phy_lcn_op_init(struct b43_wldev *dev) { struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc; b43_phy_set(dev, 0x44a, 0x80); b43_phy_mask(dev, 0x44a, 0x7f); b43_phy_set(dev, 0x6d1, 0x80); b43_phy_write(dev, 0x6d0, 0x7); b43_phy_lcn_afe_set_unset(dev); b43_phy_write(dev, 0x60a, 0xa0); b43_phy_write(dev, 0x46a, 0x19); b43_phy_maskset(dev, 0x663, 0xFF00, 0x64); b43_phy_lcn_tables_init(dev); b43_phy_lcn_rev0_baseband_init(dev); b43_phy_lcn_bu_tweaks(dev); if (dev->phy.radio_ver == 0x2064) b43_radio_2064_init(dev); else B43_WARN_ON(1); if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) b43_phy_lcn_tx_pwr_ctl_init(dev); b43_switch_channel(dev, dev->phy.channel); bcma_chipco_regctl_maskset(cc, 0, 0xf, 0x9); bcma_chipco_chipctl_maskset(cc, 0, 0, 0x03cddddd); /* TODO */ b43_phy_set(dev, 0x448, 0x4000); udelay(100); b43_phy_mask(dev, 0x448, ~0x4000); /* TODO */ return 0; }
/* Some unknown AFE (Analog Frondned) op */ static void b43_phy_ht_afe_unk1(struct b43_wldev *dev) { u8 i; const u16 ctl_regs[3][2] = { { B43_PHY_HT_AFE_CTL1, B43_PHY_HT_AFE_CTL2 }, { B43_PHY_HT_AFE_CTL3, B43_PHY_HT_AFE_CTL4 }, { B43_PHY_HT_AFE_CTL5, B43_PHY_HT_AFE_CTL6}, }; for (i = 0; i < 3; i++) { /* TODO: verify masks&sets */ b43_phy_set(dev, ctl_regs[i][1], 0x4); b43_phy_set(dev, ctl_regs[i][0], 0x4); b43_phy_mask(dev, ctl_regs[i][1], ~0x1); b43_phy_set(dev, ctl_regs[i][0], 0x1); b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0); b43_phy_mask(dev, ctl_regs[i][0], ~0x4); } }
static void b43_aphy_op_software_rfkill(struct b43_wldev *dev, bool blocked) { struct b43_phy *phy = &dev->phy; if (!blocked) { if (phy->radio_on) return; b43_radio_write16(dev, 0x0004, 0x00C0); b43_radio_write16(dev, 0x0005, 0x0008); b43_phy_mask(dev, 0x0010, 0xFFF7); b43_phy_mask(dev, 0x0011, 0xFFF7); b43_radio_init2060(dev); } else { b43_radio_write16(dev, 0x0004, 0x00FF); b43_radio_write16(dev, 0x0005, 0x00FB); b43_phy_set(dev, 0x0010, 0x0008); b43_phy_set(dev, 0x0011, 0x0008); } }
static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, u16 wait) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 save_seq_mode; int i; for (i = 0; i < 3; i++) { if (phy_ht->bb_mult_save[i] < 0) phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4)); } b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1); if (loops != 0xFFFF) loops--; b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops); b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait); save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE); b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, B43_PHY_HT_RF_SEQ_MODE_CA_OVER); /* TODO: find out mask bits! Do we need more function arguments? */ b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0); b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1); for (i = 0; i < 100; i++) { if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) { i = 0; break; } udelay(10); } if (i) b43err(dev->wl, "run samples timeout\n"); b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode); }
static void b43_phy_ht_stop_playback(struct b43_wldev *dev) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 tmp; int i; tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT); if (tmp & 0x1) b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP); else if (tmp & 0x2) b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF); b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004); for (i = 0; i < 3; i++) { if (phy_ht->bb_mult_save[i] >= 0) { b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4), phy_ht->bb_mult_save[i]); b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4), phy_ht->bb_mult_save[i]); } } }
/* wlc_radio_2064_init */ static void b43_radio_2064_init(struct b43_wldev *dev) { if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { b43_radio_write(dev, 0x09c, 0x0020); b43_radio_write(dev, 0x105, 0x0008); } else { /* TODO */ } b43_radio_write(dev, 0x032, 0x0062); b43_radio_write(dev, 0x033, 0x0019); b43_radio_write(dev, 0x090, 0x0010); b43_radio_write(dev, 0x010, 0x0000); if (dev->phy.rev == 1) { b43_radio_write(dev, 0x060, 0x007f); b43_radio_write(dev, 0x061, 0x0072); b43_radio_write(dev, 0x062, 0x007f); } b43_radio_write(dev, 0x01d, 0x0002); b43_radio_write(dev, 0x01e, 0x0006); b43_phy_write(dev, 0x4ea, 0x4688); b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2); b43_phy_mask(dev, 0x4eb, ~0x01c0); b43_phy_maskset(dev, 0x46a, 0xff00, 0x19); b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0); b43_radio_mask(dev, 0x05b, (u16) ~0xff02); b43_radio_set(dev, 0x004, 0x40); b43_radio_set(dev, 0x120, 0x10); b43_radio_set(dev, 0x078, 0x80); b43_radio_set(dev, 0x129, 0x2); b43_radio_set(dev, 0x057, 0x1); b43_radio_set(dev, 0x05b, 0x2); /* TODO: wait for some bit to be set */ b43_radio_read(dev, 0x05c); b43_radio_mask(dev, 0x05b, (u16) ~0xff02); b43_radio_mask(dev, 0x057, (u16) ~0xff01); b43_phy_write(dev, 0x933, 0x2d6b); b43_phy_write(dev, 0x934, 0x2d6b); b43_phy_write(dev, 0x935, 0x2d6b); b43_phy_write(dev, 0x936, 0x2d6b); b43_phy_write(dev, 0x937, 0x016b); b43_radio_mask(dev, 0x057, (u16) ~0xff02); b43_radio_write(dev, 0x0c2, 0x006f); }
static void b43_phy_ww(struct b43_wldev *dev) { u16 b, curr_s, best_s = 0xFFFF; int i; b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN); b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000); b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300); b43_radio_set(dev, 0x0009, 0x0080); b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002); b43_wa_initgains(dev); b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5); b = b43_phy_read(dev, B43_PHY_PWRDOWN); b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005); b43_radio_set(dev, 0x0004, 0x0004); for (i = 0x10; i <= 0x20; i++) { b43_radio_write16(dev, 0x0013, i); curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF; if (!curr_s) { best_s = 0x0000; break; } else if (curr_s >= 0x0080) curr_s = 0x0100 - curr_s; if (curr_s < best_s) best_s = curr_s; } b43_phy_write(dev, B43_PHY_PWRDOWN, b); b43_radio_mask(dev, 0x0004, 0xFFFB); b43_radio_write16(dev, 0x0013, best_s); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC); b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80); b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00); b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0); b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0); b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF); b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053); b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120); b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000); b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017); for (i = 0; i < 6; i++) b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011); b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013); b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030); b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); }
/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev, bool blocked) { if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) b43err(dev->wl, "MAC not suspended\n"); if (blocked) { b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU); } else { if (dev->phy.radio_ver == 0x2059) b43_radio_2059_init(dev); else B43_WARN_ON(1); b43_switch_channel(dev, dev->phy.channel); } }
static void b43_phy_ht_channel_setup(struct b43_wldev *dev, const struct b43_phy_ht_channeltab_e_phy *e, struct ieee80211_channel *new_channel) { bool old_band_5ghz; u8 i; old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */ if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) { /* TODO */ } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) { /* TODO */ } b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1); b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2); b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3); b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4); b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5); b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6); /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */ /* TODO: separated function? */ for (i = 0; i < 3; i++) { u16 mask; u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); if (0) /* FIXME */ mask = 0x2 << (i * 4); else mask = 0; b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)), tmp & 0xFF); b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)), tmp & 0xFF); } b43_phy_write(dev, 0x017e, 0x3830); }
static void b43_phy_ht_bphy_reset(struct b43_wldev *dev, bool reset) { u16 tmp; tmp = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp | B43_PSM_HDR_MAC_PHY_FORCE_CLK); /* Put BPHY in or take it out of the reset */ if (reset) b43_phy_set(dev, B43_PHY_B_BBCFG, B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX); else b43_phy_mask(dev, B43_PHY_B_BBCFG, (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX)); b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp); }
static void b43_phy_ht_spur_avoid(struct b43_wldev *dev, struct ieee80211_channel *new_channel) { struct bcma_device *core = dev->dev->bdev; int spuravoid = 0; u16 tmp; /* Check for 13 and 14 is just a guess, we don't have enough logs. */ if (new_channel->hw_value == 13 || new_channel->hw_value == 14) spuravoid = 1; bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false); bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid); bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_80211_PLL_REQ | B43_BCMA_CLKCTLST_PHY_PLL_REQ, B43_BCMA_CLKCTLST_80211_PLL_ST | B43_BCMA_CLKCTLST_PHY_PLL_ST, false); /* Values has been taken from wlc_bmac_switch_macfreq comments */ switch (spuravoid) { case 2: /* 126MHz */ tmp = 0x2082; break; case 1: /* 123MHz */ tmp = 0x5341; break; default: /* 120MHz */ tmp = 0x8889; } b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp); b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); /* TODO: reset PLL */ if (spuravoid) b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX); else b43_phy_mask(dev, B43_PHY_HT_BBCFG, ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF); b43_phy_ht_reset_cca(dev); }
static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev) { int i; for (i = 0; i < 3; i++) { u16 mask; u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); if (0) /* FIXME */ mask = 0x2 << (i * 4); else mask = 0; b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)), tmp & 0xFF); b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)), tmp & 0xFF); } }
static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF | B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN | B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN; static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1, B43_PHY_HT_TXPCTL_CMD_C2, B43_PHY_HT_TXPCTL_CMD_C3 }; static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1, B43_PHY_HT_TX_PCTL_STATUS_C2, B43_PHY_HT_TX_PCTL_STATUS_C3 }; int i; if (!enable) { if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) { /* We disable enabled TX pwr ctl, save it's state */ for (i = 0; i < 3; i++) phy_ht->tx_pwr_idx[i] = b43_phy_read(dev, status_regs[i]); } b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits); } else { b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits); if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { for (i = 0; i < 3; i++) b43_phy_write(dev, cmd_regs[i], 0x32); } for (i = 0; i < 3; i++) if (phy_ht->tx_pwr_idx[i] <= B43_PHY_HT_TXPCTL_CMD_C1_INIT) b43_phy_write(dev, cmd_regs[i], phy_ht->tx_pwr_idx[i]); } phy_ht->tx_pwr_ctl = enable; }
void b43_wa_initgains(struct b43_wldev *dev) { struct b43_phy *phy = &dev->phy; b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); if (phy->rev <= 2) b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); b43_radio_write16(dev, 0x0002, 0x1FBF); b43_phy_write(dev, 0x0024, 0x4680); b43_phy_write(dev, 0x0020, 0x0003); b43_phy_write(dev, 0x001D, 0x0F40); b43_phy_write(dev, 0x001F, 0x1C00); if (phy->rev <= 3) b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); else if (phy->rev == 5) { b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); b43_phy_write(dev, 0x00CC, 0x2121); } if (phy->rev >= 3) b43_phy_write(dev, 0x00BA, 0x3ED5); }
static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable) { struct b43_phy_ht *phy_ht = dev->phy.ht; u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF | B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN | B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN; static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1, B43_PHY_HT_TXPCTL_CMD_C2, B43_PHY_HT_TXPCTL_CMD_C3 }; int i; if (!enable) { if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) { /* We disable enabled TX pwr ctl, save it's state */ /* * TODO: find the registers. On N-PHY they were 0x1ed * and 0x1ee, we need 3 such a registers for HT-PHY */ } b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits); } else { b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits); if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { for (i = 0; i < 3; i++) b43_phy_write(dev, cmd_regs[i], 0x32); } for (i = 0; i < 3; i++) if (phy_ht->tx_pwr_idx[i] <= B43_PHY_HT_TXPCTL_CMD_C1_INIT) b43_phy_write(dev, cmd_regs[i], phy_ht->tx_pwr_idx[i]); } phy_ht->tx_pwr_ctl = enable; }
static void b43_phy_ht_channel_setup(struct b43_wldev *dev, const struct b43_phy_ht_channeltab_e_phy *e, struct ieee80211_channel *new_channel) { bool old_band_5ghz; old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */ if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) { /* TODO */ } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) { /* TODO */ } b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1); b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2); b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3); b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4); b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5); b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6); if (new_channel->hw_value == 14) { b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0); b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800); } else { b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, B43_PHY_HT_CLASS_CTL_OFDM_EN); if (new_channel->band == IEEE80211_BAND_2GHZ) b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840); } if (1) /* TODO: On N it's for early devices only, what about HT? */ b43_phy_ht_tx_power_fix(dev); b43_phy_ht_spur_avoid(dev, new_channel); b43_phy_write(dev, 0x017e, 0x3830); }
static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev, bool blocked) { if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) b43err(dev->wl, "MAC not suspended\n"); if (blocked) { b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00); b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00); b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00); b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2); b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808); b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8); b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8); } else { b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00); b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808); b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8); } }
static void b43_wa_divider(struct b43_wldev *dev) { b43_phy_mask(dev, 0x002B, ~0x0100); b43_phy_write(dev, 0x008E, 0x58C1); }
static int b43_phy_ht_op_init(struct b43_wldev *dev) { u16 tmp; u16 clip_state[3]; b43_phy_ht_tables_init(dev); b43_phy_mask(dev, 0x0be, ~0x2); b43_phy_set(dev, 0x23f, 0x7ff); b43_phy_set(dev, 0x240, 0x7ff); b43_phy_set(dev, 0x241, 0x7ff); b43_phy_ht_zero_extg(dev); b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3); b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0); b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0); b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0); b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20); b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20); b43_phy_write(dev, 0x20d, 0xb8); b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8); b43_phy_write(dev, 0x70, 0x50); b43_phy_write(dev, 0x1ff, 0x30); if (0) /* TODO: condition */ ; /* TODO: PHY op on reg 0x217 */ b43_phy_read(dev, 0xb0); /* TODO: what for? */ b43_phy_set(dev, 0xb0, 0x1); b43_phy_set(dev, 0xb1, 0x91); b43_phy_write(dev, 0x32f, 0x0003); b43_phy_write(dev, 0x077, 0x0010); b43_phy_write(dev, 0x0b4, 0x0258); b43_phy_mask(dev, 0x17e, ~0x4000); b43_phy_write(dev, 0x0b9, 0x0072); b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f); b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f); b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f); b43_phy_ht_afe_unk1(dev); b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111, 0x777, 0x111, 0x111, 0x777, 0x111, 0x111); b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777); b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777); b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02); b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02); b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02); b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4, 0x8e, 0x96, 0x96, 0x96); b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4, 0x8f, 0x9f, 0x9f, 0x9f); b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4, 0x8f, 0x9f, 0x9f, 0x9f); b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2); b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2); b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2); b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e); b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e); b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46); b43_phy_maskset(dev, 0x0283, 0xff00, 0x40); b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); /* TODO: Did wl mean 2 instead of 40? */ b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4, 0x09, 0x0e, 0x13, 0x18); b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd); b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd); b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd); b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1); b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1); /* Copy some tables entries */ tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144)); b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp); tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154)); b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp); tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164)); b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp); /* Reset CCA */ b43_phy_force_clock(dev, true); tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG); b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA); b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA); b43_phy_force_clock(dev, false); b43_mac_phy_clock_set(dev, true); b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX); b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX); /* TODO: PHY op on reg 0xb0 */ /* TODO: Should we restore it? Or store it in global PHY info? */ b43_phy_ht_read_clip_detection(dev, clip_state); if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) b43_phy_ht_bphy_init(dev); b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0), B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late); return 0; }
/* wlc_lcnphy_vbat_temp_sense_setup */ static void b43_phy_lcn_sense_setup(struct b43_wldev *dev, enum lcn_sense_type sense_type) { u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain; u16 auxpga_vmid; u8 tx_pwr_idx; u8 i; u16 save_radio_regs[6][2] = { { 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 }, { 0x025, 0 }, { 0x112, 0 }, }; u16 save_phy_regs[14][2] = { { 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 }, { 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 }, { 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 }, { 0x40d, 0 }, { 0x4a2, 0 }, }; u16 save_radio_4a4; msleep(1); /* Save */ for (i = 0; i < 6; i++) save_radio_regs[i][1] = b43_radio_read(dev, save_radio_regs[i][0]); for (i = 0; i < 14; i++) save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]); b43_mac_suspend(dev); save_radio_4a4 = b43_radio_read(dev, 0x4a4); /* wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF); */ tx_pwr_idx = dev->phy.lcn->tx_pwr_curr_idx; /* Setup */ /* TODO: wlc_lcnphy_set_tx_pwr_by_index(pi, 127); */ b43_radio_set(dev, 0x007, 0x1); b43_radio_set(dev, 0x0ff, 0x10); b43_radio_set(dev, 0x11f, 0x4); b43_phy_mask(dev, 0x503, ~0x1); b43_phy_mask(dev, 0x503, ~0x4); b43_phy_mask(dev, 0x4a4, ~0x4000); b43_phy_mask(dev, 0x4a4, (u16) ~0x8000); b43_phy_mask(dev, 0x4d0, ~0x20); b43_phy_set(dev, 0x4a5, 0xff); b43_phy_maskset(dev, 0x4a5, ~0x7000, 0x5000); b43_phy_mask(dev, 0x4a5, ~0x700); b43_phy_maskset(dev, 0x40d, ~0xff, 64); b43_phy_maskset(dev, 0x40d, ~0x700, 0x600); b43_phy_maskset(dev, 0x4a2, ~0xff, 64); b43_phy_maskset(dev, 0x4a2, ~0x700, 0x600); b43_phy_maskset(dev, 0x4d9, ~0x70, 0x20); b43_phy_maskset(dev, 0x4d9, ~0x700, 0x300); b43_phy_maskset(dev, 0x4d9, ~0x7000, 0x1000); b43_phy_mask(dev, 0x4da, ~0x1000); b43_phy_set(dev, 0x4da, 0x2000); b43_phy_set(dev, 0x4a6, 0x8000); b43_radio_write(dev, 0x025, 0xc); b43_radio_set(dev, 0x005, 0x8); b43_phy_set(dev, 0x938, 0x4); b43_phy_set(dev, 0x939, 0x4); b43_phy_set(dev, 0x4a4, 0x1000); /* FIXME: don't hardcode */ b43_lcntab_write(dev, B43_LCNTAB16(0x8, 0x6), 0x640); switch (sense_type) { case B43_SENSE_TEMP: b43_phy_set(dev, 0x4d7, 0x8); b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x1000); auxpga_vmidcourse = 8; auxpga_vmidfine = 0x4; auxpga_gain = 2; b43_radio_set(dev, 0x082, 0x20); break; case B43_SENSE_VBAT: b43_phy_set(dev, 0x4d7, 0x8); b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x3000); auxpga_vmidcourse = 7; auxpga_vmidfine = 0xa; auxpga_gain = 2; break; } auxpga_vmid = (0x200 | (auxpga_vmidcourse << 4) | auxpga_vmidfine); b43_phy_set(dev, 0x4d8, 0x1); b43_phy_maskset(dev, 0x4d8, ~(0x3ff << 2), auxpga_vmid << 2); b43_phy_set(dev, 0x4d8, 0x2); b43_phy_maskset(dev, 0x4d8, ~(0x7 << 12), auxpga_gain << 12); b43_phy_set(dev, 0x4d0, 0x20); b43_radio_write(dev, 0x112, 0x6); /* TODO: dummy transmission? */ /* Wait if not done */ if (!(b43_phy_read(dev, 0x476) & 0x8000)) udelay(10); /* Restore */ for (i = 0; i < 6; i++) b43_radio_write(dev, save_radio_regs[i][0], save_radio_regs[i][1]); for (i = 0; i < 14; i++) b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]); /* TODO: wlc_lcnphy_set_tx_pwr_by_index(tx_pwr_idx) */ b43_radio_write(dev, 0x4a4, save_radio_4a4); b43_mac_enable(dev); msleep(1); }