static int f3s_devices_init(void)
{
imx51_iim_register_fec_ethaddr();
imx51_add_fec(&fec_info);
imx51_add_mmc0(NULL);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_spi0(&spi_0_data);
babbage_power_init();
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
return 0;
}
static int imx51_babbage_late_init(void)
{
if (!of_machine_is_compatible("fsl,imx51-babbage"))
return 0;
babbage_power_init();
console_flush();
imx51_init_lowlevel(800);
clock_notifier_call_chain();
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start,
flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0);
return 0;
}
static int f3s_devices_init(void)
{
babbage_mmu_init();
register_device(&sdram_dev);
register_device(&fec_dev);
register_device(&esdhc_dev);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
register_device(&spi_dev);
babbage_power_init();
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
return 0;
}
static int f3s_devices_init(void)
{
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_spi0(&spi_0_data);
babbage_power_init();
console_flush();
imx51_init_lowlevel(800);
clock_notifier_call_chain();
imx51_iim_register_fec_ethaddr();
imx51_add_fec(&fec_info);
imx51_add_mmc0(NULL);
imx51_add_mmc1(NULL);
armlinux_set_bootparams((void *)0x90000100);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
return 0;
}
