/**
* @brief Initialize UART channel
*
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* @param dev UART device struct
*
* @return 0
*/
static int uart_cmsdk_apb_init(struct device *dev)
{
volatile struct uart_cmsdk_apb *uart = UART_STRUCT(dev);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
const struct uart_device_config * const dev_cfg = DEV_CFG(dev);
#endif
#ifdef CONFIG_CLOCK_CONTROL
/* Enable clock for subsystem */
struct device *clk =
device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
struct uart_cmsdk_apb_dev_data * const data = DEV_DATA(dev);
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_as);
clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_ss);
clock_control_on(clk, (clock_control_subsys_t *) &data->uart_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */
/* Set baud rate */
baudrate_set(dev);
/* Enable receiver and transmitter */
uart->ctrl = UART_RX_EN | UART_TX_EN;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
dev_cfg->irq_config_func(dev);
#endif
return 0;
}
//! initialize the uart
static void init(){
initialize_clock();
// Not using interrupts
NVIC_DisableIRQ(UART_IRQn);
// enable IO config
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); //enable IOCON
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); //enable UART
// UART I/O config
LPC_IOCON->PIO1_6 &= ~0x07;
LPC_IOCON->PIO1_6 |= 0x01; // UART RXD
LPC_IOCON->PIO1_7 &= ~0x07;
LPC_IOCON->PIO1_7 |= 0x01; // UART TXD
// Enable UART clock
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
LPC_UART->LCR = 0x83; // 8 bits, no Parity, 1 Stop bit
baudrate_set( baudrate );
LPC_UART->LCR = 0x03; // DLAB = 0
LPC_UART->FCR = 0x07; // Enable and reset TX and RX FIFO.
// Read to clear the line status.
(void)LPC_UART->LSR;
// Ensure a clean start, no data in either TX or RX FIFO.
while ( (LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
while ( LPC_UART->LSR & LSR_RDR )
{
(void)LPC_UART->RBR; // Dump data from RX FIFO
}
}
/**
* @brief Initialize UART channel
*
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* @param dev UART device struct
*
* @return 0 on success
*/
static int uart_nrf5_init(struct device *dev)
{
volatile struct _uart *uart = UART_STRUCT(dev);
struct device *gpio_dev;
gpio_dev = device_get_binding(CONFIG_GPIO_NRF5_P0_DEV_NAME);
(void) gpio_pin_configure(gpio_dev,
CONFIG_UART_NRF5_GPIO_TX_PIN,
(GPIO_DIR_OUT | GPIO_PUD_PULL_UP));
(void) gpio_pin_configure(gpio_dev,
CONFIG_UART_NRF5_GPIO_RX_PIN,
(GPIO_DIR_IN));
uart->PSELTXD = CONFIG_UART_NRF5_GPIO_TX_PIN;
uart->PSELRXD = CONFIG_UART_NRF5_GPIO_RX_PIN;
#ifdef CONFIG_UART_NRF5_FLOW_CONTROL
(void) gpio_pin_configure(gpio_dev,
CONFIG_UART_NRF5_GPIO_RTS_PIN,
(GPIO_DIR_OUT | GPIO_PUD_PULL_UP));
(void) gpio_pin_configure(gpio_dev,
CONFIG_UART_NRF5_GPIO_CTS_PIN,
(GPIO_DIR_IN));
uart->PSELRTS = CONFIG_UART_NRF5_GPIO_RTS_PIN;
uart->PSELCTS = CONFIG_UART_NRF5_GPIO_CTS_PIN;
uart->CONFIG = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
#endif /* CONFIG_UART_NRF5_FLOW_CONTROL */
DEV_DATA(dev)->baud_rate = CONFIG_UART_NRF5_BAUD_RATE;
DEV_CFG(dev)->sys_clk_freq = CONFIG_UART_NRF5_CLK_FREQ;
/* Set baud rate */
baudrate_set(dev, DEV_DATA(dev)->baud_rate,
DEV_CFG(dev)->sys_clk_freq);
/* Enable receiver and transmitter */
uart->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
uart->EVENTS_TXDRDY = 0;
uart->EVENTS_RXDRDY = 0;
uart->TASKS_STARTTX = 1;
uart->TASKS_STARTRX = 1;
dev->driver_api = &uart_nrf5_driver_api;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
DEV_CFG(dev)->irq_config_func(dev);
#endif
return 0;
}
static int usart_sam_init(struct device *dev)
{
int retval;
const struct usart_sam_dev_cfg *const cfg = DEV_CFG(dev);
struct usart_sam_dev_data *const dev_data = DEV_DATA(dev);
Usart *const usart = cfg->regs;
/* Enable USART clock in PMC */
soc_pmc_peripheral_enable(cfg->periph_id);
/* Connect pins to the peripheral */
soc_gpio_configure(&cfg->pin_rx);
soc_gpio_configure(&cfg->pin_tx);
/* Reset and disable USART */
usart->US_CR = US_CR_RSTRX | US_CR_RSTTX
| US_CR_RXDIS | US_CR_TXDIS | US_CR_RSTSTA;
/* Disable Interrupts */
usart->US_IDR = 0xFFFFFFFF;
/* 8 bits of data, no parity, 1 stop bit in normal mode */
usart->US_MR = US_MR_NBSTOP_1_BIT
| US_MR_PAR_NO
| US_MR_CHRL_8_BIT
| US_MR_USCLKS_MCK
| US_MR_CHMODE_NORMAL;
/* Set baud rate */
retval = baudrate_set(usart, dev_data->baud_rate,
SOC_ATMEL_SAM_MCK_FREQ_HZ);
if (retval != 0) {
return retval;
};
/* Enable receiver and transmitter */
usart->US_CR = US_CR_RXEN | US_CR_TXEN;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
cfg->irq_config_func(dev);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
return 0;
}
static int uarte_instance_init(struct device *dev,
const struct uarte_init_config *config,
u8_t interrupts_active)
{
int err;
NRF_UARTE_Type *uarte = get_uarte_instance(dev);
struct uarte_nrfx_data *data = get_dev_data(dev);
nrf_gpio_pin_write(config->pseltxd, 1);
nrf_gpio_cfg_output(config->pseltxd);
nrf_gpio_cfg_input(config->pselrxd, NRF_GPIO_PIN_NOPULL);
nrf_uarte_txrx_pins_set(uarte,
config->pseltxd,
config->pselrxd);
if (config->hwfc == NRF_UARTE_HWFC_ENABLED) {
nrf_gpio_pin_write(config->pselrts, 1);
nrf_gpio_cfg_output(config->pselrts);
nrf_gpio_cfg_input(config->pselcts, NRF_GPIO_PIN_NOPULL);
nrf_uarte_hwfc_pins_set(uarte,
config->pselrts,
config->pselcts);
}
/* Configure flow control and parity checking */
nrf_uarte_configure(uarte,
config->parity,
config->hwfc);
err = baudrate_set(dev, config->baudrate);
if (err) {
return err;
}
/* Enable receiver and transmitter */
nrf_uarte_enable(uarte);
nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
#if UARTE_INTERRUPT_DRIVEN
if (interrupts_active) {
/* Set ENDTX event by requesting fake (zero-length) transfer.
* Pointer to RAM variable (data->tx_buffer) is set because
* otherwise such operation may result in HardFault or RAM
* corruption.
*/
nrf_uarte_tx_buffer_set(uarte, data->tx_buffer, 0);
nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTTX);
/* switch off transmitter to save an energy */
nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STOPTX);
}
#endif /* UARTE_INTERRUPT_DRIVEN */
return 0;
}
/**
* @brief Initialize UART channel
*
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* @param dev UART device struct
*
* @return 0 on success
*/
static int uart_nrfx_init(struct device *dev)
{
struct device *gpio_dev;
int err;
gpio_dev = device_get_binding(CONFIG_GPIO_NRF5_P0_DEV_NAME);
__ASSERT(gpio_dev,
"UART init failed. Cannot find %s",
CONFIG_GPIO_NRF5_P0_DEV_NAME);
/* Setting default height state of the TX PIN to avoid glitches
* on the line during peripheral activation/deactivation.
*/
gpio_pin_write(gpio_dev, CONFIG_UART_0_NRF_TX_PIN, 1);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_TX_PIN,
GPIO_DIR_OUT);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_RX_PIN,
GPIO_DIR_IN);
nrf_uart_txrx_pins_set(NRF_UART0,
CONFIG_UART_0_NRF_TX_PIN,
CONFIG_UART_0_NRF_RX_PIN);
#ifdef CONFIG_UART_0_NRF_FLOW_CONTROL
/* Setting default height state of the RTS PIN to avoid glitches
* on the line during peripheral activation/deactivation.
*/
gpio_pin_write(gpio_dev, CONFIG_UART_0_NRF_RTS_PIN, 1);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_RTS_PIN,
GPIO_DIR_OUT);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_CTS_PIN,
GPIO_DIR_IN);
nrf_uart_hwfc_pins_set(NRF_UART0,
CONFIG_UART_0_NRF_RTS_PIN,
CONFIG_UART_0_NRF_CTS_PIN);
#endif /* CONFIG_UART_0_NRF_FLOW_CONTROL */
nrf_uart_configure(NRF_UART0,
#ifdef CONFIG_UART_0_NRF_PARITY_BIT
NRF_UART_PARITY_INCLUDED,
#else
NRF_UART_PARITY_EXCLUDED,
#endif /* CONFIG_UART_0_NRF_PARITY_BIT */
#ifdef CONFIG_UART_0_NRF_FLOW_CONTROL
NRF_UART_HWFC_ENABLED);
#else
NRF_UART_HWFC_DISABLED);
#endif /* CONFIG_UART_0_NRF_PARITY_BIT */
/* Set baud rate */
err = baudrate_set(dev, CONFIG_UART_0_BAUD_RATE);
if (err) {
return err;
}
/* Enable receiver and transmitter */
nrf_uart_enable(NRF_UART0);
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY);
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTTX);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
IRQ_CONNECT(NRFX_IRQ_NUMBER_GET(NRF_UART0),
CONFIG_UART_0_IRQ_PRI,
uart_nrfx_isr,
DEVICE_GET(uart_nrfx_uart0),
0);
irq_enable(NRFX_IRQ_NUMBER_GET(NRF_UART0));
#endif
return 0;
}
