uint16_t
AnalogPin::sample(Board::AnalogPin pin, Board::Reference ref)
{
if (sampling_pin != NULL) return (0xffffU);
loop_until_bit_is_clear(ADCSRA, ADSC);
ADMUX = (ref | (pin & 0x1f));
#if defined(MUX5)
bit_write(pin & 0x20, ADCSRB, MUX5);
#endif
bit_mask_set(ADCSRA, _BV(ADEN) | _BV(ADSC));
loop_until_bit_is_clear(ADCSRA, ADSC);
return (ADCW);
}
bool
AnalogPin::sample_request(Board::AnalogPin pin, uint8_t ref)
{
if (sampling_pin != NULL) return (false);
loop_until_bit_is_clear(ADCSRA, ADSC);
sampling_pin = this;
ADMUX = (ref | (pin & 0x1f));
#if defined(MUX5)
bit_write(pin & 0x20, ADCSRB, MUX5);
#endif
bit_mask_set(ADCSRA, _BV(ADEN) | _BV(ADSC) | _BV(ADIE));
return (true);
}
SPI::SPI() :
m_list(NULL),
m_dev(NULL),
m_busy(false)
{
// Set port data direction. Note ATtiny MOSI/MISO are DI/DO.
// Do not confuse with SPI chip programming pins
synchronized {
bit_mask_set(DDR, _BV(Board::MOSI) | _BV(Board::SCK));
bit_clear(DDR, Board::MISO);
bit_set(PORT, Board::MISO);
}
}
SPI::SPI() :
m_list(NULL),
m_dev(NULL),
m_busy(false)
{
// Initiate the SPI data direction for master mode
// The SPI/SS pin must be an output pin in master mode
synchronized {
bit_mask_set(DDRB, _BV(Board::MOSI) | _BV(Board::SCK) | _BV(Board::SS));
bit_clear(DDRB, Board::MISO);
bit_mask_clear(PORTB, _BV(Board::SCK) | _BV(Board::MOSI));
bit_set(PORTB, Board::MISO);
}
// Other the SPI setup is done by the SPI::Driver::begin()
}
SPI::SPI(uint8_t mode, Order order) :
m_list(NULL),
m_dev(NULL),
m_sem(1)
{
UNUSED(order);
// Set port data direction. Note ATtiny MOSI/MISO are DI/DO.
// Do not confuse with SPI chip programming pins
synchronized {
bit_mask_set(DDR, _BV(Board::MOSI) | _BV(Board::SCK));
bit_clear(DDR, Board::MISO);
bit_set(PORT, Board::MISO);
USICR = (_BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC));
if (mode == 1 || mode == 2) USICR |= _BV(USICS0);
}
}
SPI::Driver::Driver(Board::DigitalPin cs, Pulse pulse,
Clock rate, uint8_t mode, Order order,
Interrupt::Handler* irq) :
m_next(NULL),
m_irq(irq),
m_cs(cs, ((pulse & 0x01) == 0)),
m_pulse(pulse),
m_cpol(mode)
{
UNUSED(rate);
UNUSED(order);
// USI command for hardware supported bit banging
m_usicr = (_BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC));
if (mode == 1 || mode == 2) m_usicr |= _BV(USICS0);
// Set ports
synchronized {
bit_mask_set(DDR, _BV(Board::MOSI) | _BV(Board::SCK));
bit_clear(DDR, Board::MISO);
bit_set(PORT, Board::MISO);
USICR = m_usicr;
}
}
