static int s35390a_read_alarm(struct i2c_client *client, struct rtc_wkalrm *alm)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[3], sts;
int i, err;
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts)) < 0)
return -EIO;
sts = bitrev8(sts);
s35390a_alarm_irq_enable(client, 1);
err = s35390a_get_reg(s35390a, S35390A_CMD_INT1_REG1, buf, sizeof(buf));
if (err < 0)
return err;
/* This chip returns the bits of each byte in reverse order */
for (i = 0; i < 3; ++i) {
buf[i] = bitrev8(buf[i]);
buf[i] &= ~0x80;
}
alm->time.tm_wday = bcd2bin(buf[S35390A_ALRM_BYTE_WDAY]);
alm->time.tm_hour = s35390a_reg2hr(s35390a, buf[S35390A_ALRM_BYTE_HOURS]);
alm->time.tm_min = bcd2bin(buf[S35390A_ALRM_BYTE_MINS]);
dev_dbg(&client->dev, "%s: alm is mins=%d, hours=%d, wday=%d\n",
__func__, alm->time.tm_min, alm->time.tm_hour,
alm->time.tm_wday);
if (!(sts & BIT(2)))
s35390a_alarm_irq_enable(client, 0);
return 0;
}
void read_address(struct s_smc *smc, u_char *mac_addr)
{
char ConnectorType ;
char PmdType ;
int i ;
#ifdef PCI
for (i = 0; i < 6; i++) { /* read mac address from board */
smc->hw.fddi_phys_addr.a[i] =
bitrev8(inp(ADDR(B2_MAC_0+i)));
}
#endif
ConnectorType = inp(ADDR(B2_CONN_TYP)) ;
PmdType = inp(ADDR(B2_PMD_TYP)) ;
smc->y[PA].pmd_type[PMD_SK_CONN] =
smc->y[PB].pmd_type[PMD_SK_CONN] = ConnectorType ;
smc->y[PA].pmd_type[PMD_SK_PMD ] =
smc->y[PB].pmd_type[PMD_SK_PMD ] = PmdType ;
if (mac_addr) {
for (i = 0; i < 6 ;i++) {
smc->hw.fddi_canon_addr.a[i] = mac_addr[i] ;
smc->hw.fddi_home_addr.a[i] = bitrev8(mac_addr[i]);
}
return ;
}
smc->hw.fddi_home_addr = smc->hw.fddi_phys_addr ;
for (i = 0; i < 6 ;i++) {
smc->hw.fddi_canon_addr.a[i] =
bitrev8(smc->hw.fddi_phys_addr.a[i]);
}
}
static int __devinit mace_probe(struct platform_device *pdev)
{
int j;
struct mace_data *mp;
unsigned char *addr;
struct net_device *dev;
unsigned char checksum = 0;
int err;
dev = alloc_etherdev(PRIV_BYTES);
if (!dev)
return -ENOMEM;
mp = netdev_priv(dev);
mp->device = &pdev->dev;
SET_NETDEV_DEV(dev, &pdev->dev);
dev->base_addr = (u32)MACE_BASE;
mp->mace = MACE_BASE;
dev->irq = IRQ_MAC_MACE;
mp->dma_intr = IRQ_MAC_MACE_DMA;
mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo;
addr = (void *)MACE_PROM;
for (j = 0; j < 6; ++j) {
u8 v = bitrev8(addr[j<<4]);
checksum ^= v;
dev->dev_addr[j] = v;
}
for (; j < 8; ++j) {
checksum ^= bitrev8(addr[j<<4]);
}
if (checksum != 0xFF) {
free_netdev(dev);
return -ENODEV;
}
dev->netdev_ops = &mace_netdev_ops;
dev->watchdog_timeo = TX_TIMEOUT;
printk(KERN_INFO "%s: 68K MACE, hardware address %pM\n",
dev->name, dev->dev_addr);
err = register_netdev(dev);
if (!err)
return 0;
free_netdev(dev);
return err;
}
static int s35390a_set_alarm(struct i2c_client *client, struct rtc_wkalrm *alm)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[3], sts = 0;
int err, i;
dev_dbg(&client->dev, "%s: alm is secs=%d, mins=%d, hours=%d mday=%d, "\
"mon=%d, year=%d, wday=%d\n", __func__, alm->time.tm_sec,
alm->time.tm_min, alm->time.tm_hour, alm->time.tm_mday,
alm->time.tm_mon, alm->time.tm_year, alm->time.tm_wday);
/* disable interrupt */
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
/* clear pending interrupt, if any */
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &sts, sizeof(sts));
if (err < 0)
return err;
if (alm->enabled)
sts = S35390A_INT2_MODE_ALARM;
else
sts = S35390A_INT2_MODE_NOINTR;
/* This chip expects the bits of each byte to be in reverse order */
sts = bitrev8(sts);
/* set interupt mode*/
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
if (alm->time.tm_wday != -1)
buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
alm->time.tm_hour) | 0x80;
buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
if (alm->time.tm_hour >= 12)
buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
for (i = 0; i < 3; ++i)
buf[i] = bitrev8(buf[i]);
err = s35390a_set_reg(s35390a, S35390A_CMD_INT2_REG1, buf,
sizeof(buf));
return err;
}
static int s35390a_alarm_irq_enable(struct i2c_client *client, unsigned enabled)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
struct rtc_wkalrm *alm;
char buf[3], sts;
int err, i;
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err) {
dev_err(&client->dev, "%s: failed to read STS2 reg\n", __func__);
return err;
}
/* This chip returns the bits of each byte in reverse order */
sts = bitrev8(sts);
sts &= ~S35390A_INT1_MODE_MASK;
if (enabled)
sts |= S35390A_INT1_MODE_ALARM;
else
sts |= S35390A_INT1_MODE_NOINTR;
/* This chip returns the bits of each byte in reverse order */
sts = bitrev8(sts);
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err) {
dev_err(&client->dev, "%s: failed to set STS2 reg\n", __func__);
return err;
}
alm = &s35390a->alarm;
if (alm->time.tm_wday != -1)
buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
alm->time.tm_hour) | 0x80;
buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
if (alm->time.tm_hour >= 12)
buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
/* This chip expects the bits of each byte to be in reverse order */
for (i = 0; i < 3; ++i)
buf[i] = bitrev8(buf[i]);
return s35390a_set_reg(s35390a, S35390A_CMD_INT1_REG1, buf, sizeof(buf));
}
void smt_agent_init(struct s_smc *smc)
{
int i ;
smc->mib.m[MAC0].fddiMACSMTAddress = smc->hw.fddi_home_addr ;
smc->mib.fddiSMTStationId.sid_oem[0] = 0 ;
smc->mib.fddiSMTStationId.sid_oem[1] = 0 ;
driver_get_bia(smc,&smc->mib.fddiSMTStationId.sid_node) ;
for (i = 0 ; i < 6 ; i ++) {
smc->mib.fddiSMTStationId.sid_node.a[i] =
bitrev8(smc->mib.fddiSMTStationId.sid_node.a[i]);
}
smc->mib.fddiSMTManufacturerData[0] =
smc->mib.fddiSMTStationId.sid_node.a[0] ;
smc->mib.fddiSMTManufacturerData[1] =
smc->mib.fddiSMTStationId.sid_node.a[1] ;
smc->mib.fddiSMTManufacturerData[2] =
smc->mib.fddiSMTStationId.sid_node.a[2] ;
smc->sm.smt_tid = 0 ;
smc->mib.m[MAC0].fddiMACDupAddressTest = DA_NONE ;
smc->mib.m[MAC0].fddiMACUNDA_Flag = FALSE ;
#ifndef SLIM_SMT
smt_clear_una_dna(smc) ;
smt_clear_old_una_dna(smc) ;
#endif
for (i = 0 ; i < SMT_MAX_TEST ; i++)
smc->sm.pend[i] = 0 ;
smc->sm.please_reconnect = 0 ;
smc->sm.uniq_ticks = 0 ;
}
void driver_get_bia(struct s_smc *smc, struct fddi_addr *bia_addr)
{
int i ;
for (i = 0 ; i < 6 ; i++)
bia_addr->a[i] = bitrev8(smc->hw.fddi_phys_addr.a[i]);
}
static void s35390a_work(struct work_struct *work)
{
struct s35390a *s35390a;
struct i2c_client *client;
char buf[1];
s35390a = container_of(work, struct s35390a, work);
if (!s35390a)
return;
client = s35390a->client[0];
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
goto out;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
if (buf[0] & BIT(2)) {
/* Notify RTC core on event */
rtc_update_irq(s35390a->rtc, 1, RTC_IRQF | RTC_AF);
s35390a_alarm_irq_enable(client, 0);
} else if (buf[0] & BIT(0)) {
/* Notify RTC core on event */
rtc_update_irq(s35390a->rtc, 1, RTC_PF | RTC_IRQF);
} else if (buf[0] & BIT(1)) {
/* Notify RTC core on event */
rtc_update_irq(s35390a->rtc, 1, RTC_UF | RTC_IRQF);
}
enable_irq(client->irq);
out:
return;
}
static int get_key_isdbt(struct IR_i2c *ir, enum rc_proto *protocol,
u32 *pscancode, u8 *toggle)
{
int rc;
u8 cmd, scancode;
dev_dbg(&ir->rc->dev, "%s\n", __func__);
/* poll IR chip */
rc = i2c_master_recv(ir->c, &cmd, 1);
if (rc < 0)
return rc;
if (rc != 1)
return -EIO;
/* it seems that 0xFE indicates that a button is still hold
down, while 0xff indicates that no button is hold
down. 0xfe sequences are sometimes interrupted by 0xFF */
if (cmd == 0xff)
return 0;
scancode = bitrev8(cmd);
dev_dbg(&ir->rc->dev, "cmd %02x, scan = %02x\n", cmd, scancode);
*protocol = RC_PROTO_OTHER;
*pscancode = scancode;
*toggle = 0;
return 1;
}
/**
*@brief Write S35390A register
*/
static int s35390a_set_reg(unsigned char addr, unsigned char *dataGroup, unsigned char cnt)
{
unsigned char slaveAddress = DEVICE_ADDR;
int ret = SP_OK;
unsigned char i = 0;
int i2c_handle = 0;
addr = (addr<<1)&0x0e;
slaveAddress = (slaveAddress|addr);
i2c_handle = gp_i2c_bus_request(slaveAddress, 0x0f);
if(!i2c_handle){
DIAG_ERROR("[%s] Fail to request I2c bus!\n", __FUNCTION__);
return SP_FAIL;
}
//msb2Lsb(dataGroup, cnt);
for(i = 0; i < cnt; i++){
dataGroup[i] = bitrev8(dataGroup[i]);
}
ret = gp_i2c_bus_write(i2c_handle, dataGroup, cnt);
if(ret < 0){
DIAG_ERROR("Fail to write external RTC register!\n");
ret = SP_FAIL;
}else{
ret = SP_OK;
}
if(i2c_handle)
gp_i2c_bus_release(i2c_handle);
return ret;
}
static int s35390a_get_datetime(struct i2c_client *client, struct rtc_time *tm)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[7];
int i, err;
err = s35390a_get_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
if (err < 0)
return err;
/* This chip returns the bits of each byte in reverse order */
for (i = 0; i < 7; ++i)
buf[i] = bitrev8(buf[i]);
tm->tm_sec = bcd2bin(buf[S35390A_BYTE_SECS]);
tm->tm_min = bcd2bin(buf[S35390A_BYTE_MINS]);
tm->tm_hour = s35390a_reg2hr(s35390a, buf[S35390A_BYTE_HOURS]);
tm->tm_wday = bcd2bin(buf[S35390A_BYTE_WDAY]);
tm->tm_mday = bcd2bin(buf[S35390A_BYTE_DAY]);
tm->tm_mon = bcd2bin(buf[S35390A_BYTE_MONTH]) - 1;
tm->tm_year = bcd2bin(buf[S35390A_BYTE_YEAR]) + 100;
dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, mday=%d, "
"mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
tm->tm_wday);
return rtc_valid_tm(tm);
}
static int snd_cs8427_send_corudata(struct snd_i2c_device *device,
int udata,
unsigned char *ndata,
int count)
{
struct cs8427 *chip = device->private_data;
char *hw_data = udata ?
chip->playback.hw_udata : chip->playback.hw_status;
char data[32];
int err, idx;
if (!memcmp(hw_data, ndata, count))
return 0;
if ((err = snd_cs8427_select_corudata(device, udata)) < 0)
return err;
memcpy(hw_data, ndata, count);
if (udata) {
memset(data, 0, sizeof(data));
if (memcmp(hw_data, data, count) == 0) {
chip->regmap[CS8427_REG_UDATABUF] &= ~CS8427_UBMMASK;
chip->regmap[CS8427_REG_UDATABUF] |= CS8427_UBMZEROS |
CS8427_EFTUI;
err = snd_cs8427_reg_write(device, CS8427_REG_UDATABUF,
chip->regmap[CS8427_REG_UDATABUF]);
return err < 0 ? err : 0;
}
}
data[0] = CS8427_REG_AUTOINC | CS8427_REG_CORU_DATABUF;
for (idx = 0; idx < count; idx++)
data[idx + 1] = bitrev8(ndata[idx]);
if (snd_i2c_sendbytes(device, data, count + 1) != count + 1)
return -EIO;
return 1;
}
static int s35390a_set_datetime(struct i2c_client *client, struct rtc_time *tm)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
int i, err;
char buf[7];
dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d mday=%d, "
"mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
tm->tm_wday);
buf[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 100);
buf[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon + 1);
buf[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
buf[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
buf[S35390A_BYTE_HOURS] = s35390a_hr2reg(s35390a, tm->tm_hour);
buf[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
buf[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
/* This chip expects the bits of each byte to be in reverse order */
for (i = 0; i < 7; ++i)
buf[i] = bitrev8(buf[i]);
err = s35390a_set_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
return err;
}
static inline void bit_reverse_addr(unsigned char addr[6])
{
int i;
for(i = 0; i < 6; i++)
addr[i] = bitrev8(addr[i]);
}
static int usb6fire_fw_fpga_upload(
struct usb_interface *intf, const char *fwname)
{
int ret;
int i;
struct usb_device *device = interface_to_usbdev(intf);
u8 *buffer = kmalloc(FPGA_BUFSIZE, GFP_KERNEL);
const char *c;
const char *end;
const struct firmware *fw;
if (!buffer)
return -ENOMEM;
ret = request_firmware(&fw, fwname, &device->dev);
if (ret < 0) {
dev_err(&intf->dev, "unable to get fpga firmware %s.\n",
fwname);
kfree(buffer);
return -EIO;
}
c = fw->data;
end = fw->data + fw->size;
ret = usb6fire_fw_ezusb_write(device, 8, 0, NULL, 0);
if (ret < 0) {
kfree(buffer);
release_firmware(fw);
dev_err(&intf->dev,
"unable to upload fpga firmware: begin urb.\n");
return ret;
}
while (c != end) {
for (i = 0; c != end && i < FPGA_BUFSIZE; i++, c++)
buffer[i] = bitrev8((u8)*c);
ret = usb6fire_fw_fpga_write(device, buffer, i);
if (ret < 0) {
release_firmware(fw);
kfree(buffer);
dev_err(&intf->dev,
"unable to upload fpga firmware: fw urb.\n");
return ret;
}
}
release_firmware(fw);
kfree(buffer);
ret = usb6fire_fw_ezusb_write(device, 9, 0, NULL, 0);
if (ret < 0) {
dev_err(&intf->dev,
"unable to upload fpga firmware: end urb.\n");
return ret;
}
return 0;
}
static int s35390a_freq_irq_enable(struct i2c_client *client, unsigned enabled)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[1];
int err;
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
if (err) {
dev_err(&client->dev, "%s: failed to read STS2 reg\n", __func__);
return err;
}
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
buf[0] &= ~S35390A_INT1_MODE_MASK;
if (enabled)
buf[0] |= S35390A_INT1_MODE_FREQ;
else
buf[0] |= S35390A_INT1_MODE_NOINTR;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
if (err) {
dev_err(&client->dev, "%s: failed to set STS2 reg\n", __func__);
return err;
}
if (enabled) {
buf[0] = s35390a->rtc->irq_freq;
buf[0] = bitrev8(buf[0]);
err = s35390a_set_reg(s35390a, S35390A_CMD_INT1_REG1, buf,
sizeof(buf));
}
return err;
}
static int s35390a_update_irq_enable(struct i2c_client *client, unsigned enabled)
{
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[1];
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
return -EIO;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
buf[0] &= ~S35390A_INT1_MODE_MASK;
if (enabled)
buf[0] |= S35390A_INT1_MODE_PMIN_EDG;
else
buf[0] |= S35390A_INT1_MODE_NOINTR;
/* This chip returns the bits of each byte in reverse order */
buf[0] = bitrev8(buf[0]);
return s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
}
static int ws_eink_update_display(struct ws_eink_fb_par *par)
{
int ret = 0;
int i;
int frame_size;
u8 *vmem = par->info->screen_base;
u8 *ssbuf = par->ssbuf;
const u8 *lut;
size_t lut_size;
static int update_count = 0;
if(++update_count == 10) {
update_count = 0;
lut = lut_full_update;
lut_size = ARRAY_SIZE(lut_full_update);
} else {
lut = lut_partial_update;
lut_size = ARRAY_SIZE(lut_partial_update);
}
ret = int_lut(par, lut, lut_size);
if (ret)
return ret;
frame_size = par->props->height * par->props->width * par->props->bpp / 8;
memcpy(ssbuf, vmem, frame_size);
for (i = 0; i < frame_size; i++) {
ssbuf[i] = bitrev8(ssbuf[i]);
}
ret = set_frame_memory(par, ssbuf);
if (ret)
return ret;
ret = display_frame(par);
if (ret)
return ret;
ret = ws_eink_sleep(par);
return ret;
}
static void
wbcir_shutdown(struct pnp_dev *device)
{
struct device *dev = &device->dev;
struct wbcir_data *data = pnp_get_drvdata(device);
bool do_wake = true;
u8 match[11];
u8 mask[11];
u8 rc6_csl = 0;
int i;
memset(match, 0, sizeof(match));
memset(mask, 0, sizeof(mask));
if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
do_wake = false;
goto finish;
}
switch (protocol) {
case IR_PROTOCOL_RC5:
if (wake_sc > 0xFFF) {
do_wake = false;
dev_err(dev, "RC5 - Invalid wake scancode\n");
break;
}
/* Mask = 13 bits, ex toggle */
mask[0] = 0xFF;
mask[1] = 0x17;
match[0] = (wake_sc & 0x003F); /* 6 command bits */
match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
if (!(wake_sc & 0x0040)) /* 2nd start bit */
match[1] |= 0x10;
break;
case IR_PROTOCOL_NEC:
if (wake_sc > 0xFFFFFF) {
do_wake = false;
dev_err(dev, "NEC - Invalid wake scancode\n");
break;
}
mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
match[1] = bitrev8((wake_sc & 0xFF));
match[0] = ~match[1];
match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
if (wake_sc > 0xFFFF)
match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
else
match[2] = ~match[3];
break;
case IR_PROTOCOL_RC6:
if (wake_rc6mode == 0) {
if (wake_sc > 0xFFFF) {
do_wake = false;
dev_err(dev, "RC6 - Invalid wake scancode\n");
break;
}
/* Command */
match[0] = wbcir_to_rc6cells(wake_sc >> 0);
mask[0] = 0xFF;
match[1] = wbcir_to_rc6cells(wake_sc >> 4);
mask[1] = 0xFF;
/* Address */
match[2] = wbcir_to_rc6cells(wake_sc >> 8);
mask[2] = 0xFF;
match[3] = wbcir_to_rc6cells(wake_sc >> 12);
mask[3] = 0xFF;
/* Header */
match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
mask[4] = 0xF0;
match[5] = 0x09; /* start bit = 1, mode2 = 0 */
mask[5] = 0x0F;
rc6_csl = 44;
} else if (wake_rc6mode == 6) {
static int mace_probe(struct platform_device *pdev)
{
int j;
struct mace_data *mp;
unsigned char *addr;
struct net_device *dev;
unsigned char checksum = 0;
int err;
dev = alloc_etherdev(PRIV_BYTES);
if (!dev)
return -ENOMEM;
mp = netdev_priv(dev);
mp->device = &pdev->dev;
SET_NETDEV_DEV(dev, &pdev->dev);
dev->base_addr = (u32)MACE_BASE;
mp->mace = MACE_BASE;
dev->irq = IRQ_MAC_MACE;
mp->dma_intr = IRQ_MAC_MACE_DMA;
mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo;
/*
* The PROM contains 8 bytes which total 0xFF when XOR'd
* together. Due to the usual peculiar apple brain damage
* the bytes are spaced out in a strange boundary and the
* bits are reversed.
*/
addr = MACE_PROM;
for (j = 0; j < 6; ++j) {
u8 v = bitrev8(addr[j<<4]);
checksum ^= v;
dev->dev_addr[j] = v;
}
for (; j < 8; ++j) {
checksum ^= bitrev8(addr[j<<4]);
}
if (checksum != 0xFF) {
free_netdev(dev);
return -ENODEV;
}
dev->netdev_ops = &mace_netdev_ops;
dev->watchdog_timeo = TX_TIMEOUT;
printk(KERN_INFO "%s: 68K MACE, hardware address %pM\n",
dev->name, dev->dev_addr);
err = register_netdev(dev);
if (!err)
return 0;
free_netdev(dev);
return err;
}
/*
isdnhdlc_decode - decodes HDLC frames from a transparent bit stream.
The source buffer is scanned for valid HDLC frames looking for
flags (01111110) to indicate the start of a frame. If the start of
the frame is found, the bit stuffing is removed (0 after 5 1's).
When a new flag is found, the complete frame has been received
and the CRC is checked.
If a valid frame is found, the function returns the frame length
excluding the CRC with the bit HDLC_END_OF_FRAME set.
If the beginning of a valid frame is found, the function returns
the length.
If a framing error is found (too many 1s and not a flag) the function
returns the length with the bit HDLC_FRAMING_ERROR set.
If a CRC error is found the function returns the length with the
bit HDLC_CRC_ERROR set.
If the frame length exceeds the destination buffer size, the function
returns the length with the bit HDLC_LENGTH_ERROR set.
src - source buffer
slen - source buffer length
count - number of bytes removed (decoded) from the source buffer
dst _ destination buffer
dsize - destination buffer size
returns - number of decoded bytes in the destination buffer and status
flag.
*/
int isdnhdlc_decode(struct isdnhdlc_vars *hdlc, const u8 *src, int slen,
int *count, u8 *dst, int dsize)
{
int status = 0;
static const unsigned char fast_flag[] = {
0x00, 0x00, 0x00, 0x20, 0x30, 0x38, 0x3c, 0x3e, 0x3f
};
static const unsigned char fast_flag_value[] = {
0x00, 0x7e, 0xfc, 0xf9, 0xf3, 0xe7, 0xcf, 0x9f, 0x3f
};
static const unsigned char fast_abort[] = {
0x00, 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff
};
#define handle_fast_flag(h) \
do { \
if (h->cbin == fast_flag[h->bit_shift]) { \
h->ffvalue = fast_flag_value[h->bit_shift]; \
h->state = HDLC_FAST_FLAG; \
h->ffbit_shift = h->bit_shift; \
h->bit_shift = 1; \
} else { \
h->state = HDLC_GET_DATA; \
h->data_received = 0; \
} \
} while (0)
#define handle_abort(h) \
do { \
h->shift_reg = fast_abort[h->ffbit_shift - 1]; \
h->hdlc_bits1 = h->ffbit_shift - 2; \
if (h->hdlc_bits1 < 0) \
h->hdlc_bits1 = 0; \
h->data_bits = h->ffbit_shift - 1; \
h->state = HDLC_GET_DATA; \
h->data_received = 0; \
} while (0)
*count = slen;
while (slen > 0) {
if (hdlc->bit_shift == 0) {
/* the code is for bitreverse streams */
if (hdlc->do_bitreverse == 0)
hdlc->cbin = bitrev8(*src++);
else
hdlc->cbin = *src++;
slen--;
hdlc->bit_shift = 8;
if (hdlc->do_adapt56)
hdlc->bit_shift--;
}
switch (hdlc->state) {
case STOPPED:
return 0;
case HDLC_FAST_IDLE:
if (hdlc->cbin == 0xff) {
hdlc->bit_shift = 0;
break;
}
hdlc->state = HDLC_GET_FLAG_B0;
hdlc->hdlc_bits1 = 0;
hdlc->bit_shift = 8;
break;
case HDLC_GET_FLAG_B0:
if (!(hdlc->cbin & 0x80)) {
hdlc->state = HDLC_GETFLAG_B1A6;
hdlc->hdlc_bits1 = 0;
} else {
if ((!hdlc->do_adapt56) &&
(++hdlc->hdlc_bits1 >= 8) &&
(hdlc->bit_shift == 1))
hdlc->state = HDLC_FAST_IDLE;
}
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GETFLAG_B1A6:
if (hdlc->cbin & 0x80) {
hdlc->hdlc_bits1++;
if (hdlc->hdlc_bits1 == 6)
hdlc->state = HDLC_GETFLAG_B7;
} else
hdlc->hdlc_bits1 = 0;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GETFLAG_B7:
if (hdlc->cbin & 0x80) {
hdlc->state = HDLC_GET_FLAG_B0;
} else {
hdlc->state = HDLC_GET_DATA;
hdlc->crc = 0xffff;
hdlc->shift_reg = 0;
hdlc->hdlc_bits1 = 0;
hdlc->data_bits = 0;
hdlc->data_received = 0;
}
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_GET_DATA:
if (hdlc->cbin & 0x80) {
hdlc->hdlc_bits1++;
switch (hdlc->hdlc_bits1) {
case 6:
break;
case 7:
if (hdlc->data_received)
/* bad frame */
status = -HDLC_FRAMING_ERROR;
if (!hdlc->do_adapt56) {
if (hdlc->cbin == fast_abort
[hdlc->bit_shift + 1]) {
hdlc->state =
HDLC_FAST_IDLE;
hdlc->bit_shift = 1;
break;
}
} else
hdlc->state = HDLC_GET_FLAG_B0;
break;
default:
hdlc->shift_reg >>= 1;
hdlc->shift_reg |= 0x80;
hdlc->data_bits++;
break;
}
} else {
switch (hdlc->hdlc_bits1) {
case 5:
break;
case 6:
if (hdlc->data_received)
status = check_frame(hdlc);
hdlc->crc = 0xffff;
hdlc->shift_reg = 0;
hdlc->data_bits = 0;
if (!hdlc->do_adapt56)
handle_fast_flag(hdlc);
else {
hdlc->state = HDLC_GET_DATA;
hdlc->data_received = 0;
}
break;
default:
hdlc->shift_reg >>= 1;
hdlc->data_bits++;
break;
}
hdlc->hdlc_bits1 = 0;
}
if (status) {
hdlc->dstpos = 0;
*count -= slen;
hdlc->cbin <<= 1;
hdlc->bit_shift--;
return status;
}
if (hdlc->data_bits == 8) {
hdlc->data_bits = 0;
hdlc->data_received = 1;
hdlc->crc = crc_ccitt_byte(hdlc->crc,
hdlc->shift_reg);
/* good byte received */
if (hdlc->dstpos < dsize)
dst[hdlc->dstpos++] = hdlc->shift_reg;
else {
/* frame too long */
status = -HDLC_LENGTH_ERROR;
hdlc->dstpos = 0;
}
}
hdlc->cbin <<= 1;
hdlc->bit_shift--;
break;
case HDLC_FAST_FLAG:
if (hdlc->cbin == hdlc->ffvalue) {
hdlc->bit_shift = 0;
break;
} else {
if (hdlc->cbin == 0xff) {
hdlc->state = HDLC_FAST_IDLE;
hdlc->bit_shift = 0;
} else if (hdlc->ffbit_shift == 8) {
hdlc->state = HDLC_GETFLAG_B7;
break;
} else
handle_abort(hdlc);
}
break;
default:
break;
}
/**
* ir_sony_decode() - Decode one Sony pulse or space
* @input_dev: the struct input_dev descriptor of the device
* @ev: the struct ir_raw_event descriptor of the pulse/space
*
* This function returns -EINVAL if the pulse violates the state machine
*/
static int ir_sony_decode(struct input_dev *input_dev, struct ir_raw_event ev)
{
struct ir_input_dev *ir_dev = input_get_drvdata(input_dev);
struct sony_dec *data = &ir_dev->raw->sony;
u32 scancode;
u8 device, subdevice, function;
if (!(ir_dev->raw->enabled_protocols & IR_TYPE_SONY))
return 0;
if (IS_RESET(ev)) {
data->state = STATE_INACTIVE;
return 0;
}
if (!geq_margin(ev.duration, SONY_UNIT, SONY_UNIT / 2))
goto out;
IR_dprintk(2, "Sony decode started at state %d (%uus %s)\n",
data->state, TO_US(ev.duration), TO_STR(ev.pulse));
switch (data->state) {
case STATE_INACTIVE:
if (!ev.pulse)
break;
if (!eq_margin(ev.duration, SONY_HEADER_PULSE, SONY_UNIT / 2))
break;
data->count = 0;
data->state = STATE_HEADER_SPACE;
return 0;
case STATE_HEADER_SPACE:
if (ev.pulse)
break;
if (!eq_margin(ev.duration, SONY_HEADER_SPACE, SONY_UNIT / 2))
break;
data->state = STATE_BIT_PULSE;
return 0;
case STATE_BIT_PULSE:
if (!ev.pulse)
break;
data->bits <<= 1;
if (eq_margin(ev.duration, SONY_BIT_1_PULSE, SONY_UNIT / 2))
data->bits |= 1;
else if (!eq_margin(ev.duration, SONY_BIT_0_PULSE, SONY_UNIT / 2))
break;
data->count++;
data->state = STATE_BIT_SPACE;
return 0;
case STATE_BIT_SPACE:
if (ev.pulse)
break;
if (!geq_margin(ev.duration, SONY_BIT_SPACE, SONY_UNIT / 2))
break;
decrease_duration(&ev, SONY_BIT_SPACE);
if (!geq_margin(ev.duration, SONY_UNIT, SONY_UNIT / 2)) {
data->state = STATE_BIT_PULSE;
return 0;
}
data->state = STATE_FINISHED;
/* Fall through */
case STATE_FINISHED:
if (ev.pulse)
break;
if (!geq_margin(ev.duration, SONY_TRAILER_SPACE, SONY_UNIT / 2))
break;
switch (data->count) {
case 12:
device = bitrev8((data->bits << 3) & 0xF8);
subdevice = 0;
function = bitrev8((data->bits >> 4) & 0xFE);
break;
case 15:
device = bitrev8((data->bits >> 0) & 0xFF);
subdevice = 0;
function = bitrev8((data->bits >> 7) & 0xFD);
break;
case 20:
device = bitrev8((data->bits >> 5) & 0xF8);
subdevice = bitrev8((data->bits >> 0) & 0xFF);
function = bitrev8((data->bits >> 12) & 0xFE);
break;
default:
IR_dprintk(1, "Sony invalid bitcount %u\n", data->count);
goto out;
}
scancode = device << 16 | subdevice << 8 | function;
IR_dprintk(1, "Sony(%u) scancode 0x%05x\n", data->count, scancode);
ir_keydown(input_dev, scancode, 0);
data->state = STATE_INACTIVE;
return 0;
}
out:
IR_dprintk(1, "Sony decode failed at state %d (%uus %s)\n",
data->state, TO_US(ev.duration), TO_STR(ev.pulse));
data->state = STATE_INACTIVE;
return -EINVAL;
}
/*
* Encode and transmit next frame.
*/
static void usb_b_out(struct st5481_bcs *bcs,int buf_nr)
{
struct st5481_b_out *b_out = &bcs->b_out;
struct st5481_adapter *adapter = bcs->adapter;
struct urb *urb;
unsigned int packet_size,offset;
int len,buf_size,bytes_sent;
int i;
struct sk_buff *skb;
if (test_and_set_bit(buf_nr, &b_out->busy)) {
DBG(4,"ep %d urb %d busy",(bcs->channel+1)*2,buf_nr);
return;
}
urb = b_out->urb[buf_nr];
// Adjust isoc buffer size according to flow state
if(b_out->flow_event & (OUT_DOWN | OUT_UNDERRUN)) {
buf_size = NUM_ISO_PACKETS_B*SIZE_ISO_PACKETS_B_OUT + B_FLOW_ADJUST;
packet_size = SIZE_ISO_PACKETS_B_OUT + B_FLOW_ADJUST;
DBG(4,"B%d,adjust flow,add %d bytes",bcs->channel+1,B_FLOW_ADJUST);
} else if(b_out->flow_event & OUT_UP){
buf_size = NUM_ISO_PACKETS_B*SIZE_ISO_PACKETS_B_OUT - B_FLOW_ADJUST;
packet_size = SIZE_ISO_PACKETS_B_OUT - B_FLOW_ADJUST;
DBG(4,"B%d,adjust flow,remove %d bytes",bcs->channel+1,B_FLOW_ADJUST);
} else {
buf_size = NUM_ISO_PACKETS_B*SIZE_ISO_PACKETS_B_OUT;
packet_size = 8;
}
b_out->flow_event = 0;
len = 0;
while (len < buf_size) {
if ((skb = b_out->tx_skb)) {
DBG_SKB(0x100, skb);
DBG(4,"B%d,len=%d",bcs->channel+1,skb->len);
if (bcs->mode == L1_MODE_TRANS) {
bytes_sent = buf_size - len;
if (skb->len < bytes_sent)
bytes_sent = skb->len;
{ /* swap tx bytes to get hearable audio data */
register unsigned char *src = skb->data;
register unsigned char *dest = urb->transfer_buffer+len;
register unsigned int count;
for (count = 0; count < bytes_sent; count++)
*dest++ = bitrev8(*src++);
}
len += bytes_sent;
} else {
len += isdnhdlc_encode(&b_out->hdlc_state,
skb->data, skb->len, &bytes_sent,
urb->transfer_buffer+len, buf_size-len);
}
skb_pull(skb, bytes_sent);
if (!skb->len) {
// Frame sent
b_out->tx_skb = NULL;
B_L1L2(bcs, PH_DATA | CONFIRM, (void *)(unsigned long) skb->truesize);
dev_kfree_skb_any(skb);
/* if (!(bcs->tx_skb = skb_dequeue(&bcs->sq))) { */
/* st5481B_sched_event(bcs, B_XMTBUFREADY); */
/* } */
}
} else {
if (bcs->mode == L1_MODE_TRANS) {
memset(urb->transfer_buffer+len, 0xff, buf_size-len);
len = buf_size;
} else {
// Send flags
len += isdnhdlc_encode(&b_out->hdlc_state,
NULL, 0, &bytes_sent,
urb->transfer_buffer+len, buf_size-len);
}
}
}
// Prepare the URB
for (i = 0, offset = 0; offset < len; i++) {
urb->iso_frame_desc[i].offset = offset;
urb->iso_frame_desc[i].length = packet_size;
offset += packet_size;
packet_size = SIZE_ISO_PACKETS_B_OUT;
}
urb->transfer_buffer_length = len;
urb->number_of_packets = i;
urb->dev = adapter->usb_dev;
DBG_ISO_PACKET(0x200,urb);
SUBMIT_URB(urb, GFP_NOIO);
}
static int __devinit mace_probe(struct platform_device *pdev)
{
int j;
struct mace_data *mp;
unsigned char *addr;
struct net_device *dev;
unsigned char checksum = 0;
static int found = 0;
int err;
if (found || macintosh_config->ether_type != MAC_ETHER_MACE)
return -ENODEV;
found = 1; /* prevent 'finding' one on every device probe */
dev = alloc_etherdev(PRIV_BYTES);
if (!dev)
return -ENOMEM;
mp = netdev_priv(dev);
mp->device = &pdev->dev;
SET_NETDEV_DEV(dev, &pdev->dev);
SET_MODULE_OWNER(dev);
dev->base_addr = (u32)MACE_BASE;
mp->mace = (volatile struct mace *) MACE_BASE;
dev->irq = IRQ_MAC_MACE;
mp->dma_intr = IRQ_MAC_MACE_DMA;
mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo;
/*
* The PROM contains 8 bytes which total 0xFF when XOR'd
* together. Due to the usual peculiar apple brain damage
* the bytes are spaced out in a strange boundary and the
* bits are reversed.
*/
addr = (void *)MACE_PROM;
for (j = 0; j < 6; ++j) {
u8 v = bitrev8(addr[j<<4]);
checksum ^= v;
dev->dev_addr[j] = v;
}
for (; j < 8; ++j) {
checksum ^= bitrev8(addr[j<<4]);
}
if (checksum != 0xFF) {
free_netdev(dev);
return -ENODEV;
}
memset(&mp->stats, 0, sizeof(mp->stats));
dev->open = mace_open;
dev->stop = mace_close;
dev->hard_start_xmit = mace_xmit_start;
dev->tx_timeout = mace_tx_timeout;
dev->watchdog_timeo = TX_TIMEOUT;
dev->get_stats = mace_stats;
dev->set_multicast_list = mace_set_multicast;
dev->set_mac_address = mace_set_address;
printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]);
for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]);
printk("\n");
err = register_netdev(dev);
if (!err)
return 0;
free_netdev(dev);
return err;
}