/**
* \brief Main application loop
*
* This is the main application function, which runs all the initialization
* code, clears the display and enters a loop in which it continuously polls
* for new messages from the maXTouch device. If one or more messages are
* pending, the maXTouch message handler is invoked.
*/
int main(void)
{
/* maXTouch data structure */
static struct mxt_device device;
/* Basic init routines */
board_init();
sysclk_init();
gfx_init();
mxt_init(&device);
/* Draw the paint pallet to the display */
draw_paint_pallet();
/* Draw instructions to the display */
gfx_draw_string_aligned(
"Select a color from the pallet below, and\n"
"use your finger(s) to draw onto the display.\n\n"
"Multiple simultaneous fingers are supported,\n"
"and the drawing size varies according to the\n"
"pressure of the touch.\n\n"
"Select MUL to draw using multiple colors.\n\n"
"Select CLR to clear the display.",
gfx_get_width() / 2,
(gfx_get_height() - PALLET_HEIGHT) / 2,
&sysfont, GFX_COLOR_TRANSPARENT, GFX_COLOR_WHITE,
TEXT_POS_CENTER, TEXT_ALIGN_LEFT);
while (true) {
/* Check for any pending messages and run message handler if any
* message is found in the queue */
if (mxt_is_message_pending(&device)) {
mxt_handler(&device);
}
}
}
/*! \brief Main function.
*/
int main(void)
{
sysclk_init();
/* Initialize the board.
* The board-specific conf_board.h file contains the configuration of
* the board initialization.
*/
board_init();
/* Config the USART_SPI in master mode. */
usart_spi_init(USART_SPI_EXAMPLE);
usart_spi_setup_device(USART_SPI_EXAMPLE, &USART_SPI_DEVICE_EXAMPLE,
SPI_MODE_0, USART_SPI_EXAMPLE_BAUDRATE, 0);
usart_spi_enable(USART_SPI_EXAMPLE);
/* Config the SPI module in slave mode. */
spi_slave_init(SPI_SLAVE_EXAMPLE, SPI_MODE_0);
spi_enable(SPI_SLAVE_EXAMPLE);
/* Enable global interrupt */
cpu_irq_enable();
/* Show the test result by LED. */
if (spi_usart_master_transfer() == true && spi_slave_transfer() ==
true) {
ioport_set_pin_level(SPI_SLAVE_EXAMPLE_LED_PIN,
IOPORT_PIN_LEVEL_LOW);
} else {
ioport_set_pin_level(SPI_SLAVE_EXAMPLE_LED_PIN,
IOPORT_PIN_LEVEL_HIGH);
}
while (1) {
/* Do nothing */
}
}
/**
* \brief main function
*/
int main (void)
{
/* Initialize basic board support features.
* - Initialize system clock sources according to device-specific
* configuration parameters supplied in a conf_clock.h file.
* - Set up GPIO and board-specific features using additional configuration
* parameters, if any, specified in a conf_board.h file.
*/
sysclk_init();
board_init();
// Initialize interrupt vector table support.
irq_initialize_vectors();
// Enable interrupts
cpu_irq_enable();
/* Call a local utility routine to initialize C-Library Standard I/O over
* a USB CDC protocol. Tunable parameters in a conf_usb.h file must be
* supplied to configure the USB device correctly.
*/
stdio_usb_init();
// Get and echo characters forever.
uint8_t ch;
while (true) {
scanf("%c",&ch); // get one input character
if (ch) {
printf("%c",ch); // echo to output
}
}
}
void init()
{
// board init
board_init();
#if UC3L
// clock frequencies
#define EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 // DFLL target frequency, in Hz
#define EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 // MCU clock target frequency, in Hz
#define EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 // PBA clock target frequency, in Hz
// parameters to pcl_configure_clocks().
static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, false};
static pcl_freq_param_t pcl_dfll_freq_param = {
.main_clk_src = PCL_MC_DFLL0,
.cpu_f = EXAMPLE_TARGET_MCUCLK_FREQ_HZ,
.pba_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ,
.pbb_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ,
.dfll_f = EXAMPLE_TARGET_DFLL_FREQ_HZ,
.pextra_params = &gc_dfllif_ref_opt
};
pcl_configure_clocks(&pcl_dfll_freq_param);
#else
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
#endif
// stdio init
stdio_usb_init(&CONFIG_USART_IF);
// Specify that stdout and stdin should not be buffered.
#if defined(__GNUC__) && defined(__AVR32__)
setbuf(stdout, NULL);
setbuf(stdin, NULL);
#endif
}
/*! \brief Main function. Execution starts here.
*/
int main(void)
{
irq_initialize_vectors();
cpu_irq_enable();
/* Initialize ASF services */
sleepmgr_init();
sysclk_init();
board_init();
gfx_mono_init();
sd_mmc_init();
rtc_init();
stdio_usb_init(); /* Initialize STDIO and start USB */
udc_stop(); /* Stop USB by default */
main_introduction();
/* Initialize tasks */
app_touch_init();
app_cpu_load_init();
app_sampling_init();
/* The main loop */
while (true) {
/* Enter in sleep mode */
app_cpu_load_enter_sleep();
sleepmgr_enter_sleep();
/* Execute tasks */
app_usb_task();
app_microsd_task();
app_sampling_task();
app_touch_task();
app_cpu_load_task();
}
}
/**
* \brief Run ABDAC driver unit tests.
*/
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
/* Define all the test cases. */
DEFINE_TEST_CASE(abdac_init_test, NULL, run_abdac_init_test, NULL,
"SAM ABDAC initialization test.");
DEFINE_TEST_CASE(abdac_interrupt_test, NULL, run_abdac_interrupt_test,
NULL, "SAM ABDAC interrupt test.");
/* Put test case addresses in an array. */
DEFINE_TEST_ARRAY(abdac_tests) = {
&abdac_init_test,
&abdac_interrupt_test,
};
/* Define the test suite. */
DEFINE_TEST_SUITE(abdac_suite, abdac_tests,
"SAM ABDAC driver test suite");
/* Run all tests in the test suite. */
test_suite_run(&abdac_suite);
while (1) {
/* Busy-wait forever. */
}
}
/**
* \brief Application entry point for usart_dmac_serial example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* Initialize the SAM system. */
sysclk_init();
board_init();
/* Configure UART for debug message output. */
configure_console();
/* Output example information. */
puts(STRING_HEADER);
/* Configure USART. */
configure_usart();
/* Configure DMAC. */
configure_dmac();
/* Configure DMAC RX channel. */
configure_dmac_rx();
while (1) {
}
}
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS,
};
/* Usual initializations */
board_init();
sysclk_init();
sleepmgr_init();
irq_initialize_vectors();
cpu_irq_enable();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
printf("\x0C\n\r-- ADC Calibration Example");
printf(" (Compiled: %s %s)\n\r", __DATE__, __TIME__);
/* ADC and DAC initializations */
main_dac_init();
main_adc_init();
printf("\n\rConversion samples without correction:\n\r");
main_conversions();
/* Measure and enable corrections */
main_adc_correction();
printf("Conversion samples with correction:\n\r");
main_conversions();
while (1) {
}
}
/*
* ip7500module_init
* Called to add the devices which we have on this board
*/
static int __init ip7500module_init(void)
{
if (ubicom32_flash_single_init()) {
printk(KERN_ERR "%s: could not initialize flash controller\n", __FUNCTION__);
}
board_init();
ubi_gpio_init();
/*
* Start the flash driver
*/
ubicom32_flash_single_init();
platform_add_devices(ip7500module_devices, ARRAY_SIZE(ip7500module_devices));
printk(KERN_INFO "%s: registering i2c resources\n", __FUNCTION__);
i2c_register_board_info(0, ip7500module_i2c_board_info, ARRAY_SIZE(ip7500module_i2c_board_info));
//vdc_tio_init(NULL);
return 0;
}
/**
* \brief Main program function. Configure the hardware, initialize lwIP
* TCP/IP stack, and start HTTP service.
*/
int main(void)
{
/* Initialize the SAM system. */
sysclk_init();
board_init();
/* Configure debug UART */
configure_console();
/* Print example information. */
puts(STRING_HEADER);
/* Bring up the ethernet interface & initialize timer0, channel0. */
init_ethernet();
/* Bring up the web server. */
httpd_init();
/* Program main loop. */
while (1) {
/* Check for input packet and process it. */
ethernet_task();
}
}
/**
* Main function, initialization and main message loop
*
*/
int main (void)
{
irq_initialize_vectors();
/* Initialize the board.
* The board-specific conf_board.h file contains the configuration of
* the board initialization.
*/
sysclk_init();
board_init();
sw_timer_init();
if (nwk_init()!= NWK_SUCCESS)
{
app_alert();
}
zid_indication_callback_init();
/*
* The stack is initialized above, hence the global interrupts are enabled
* here.
*/
cpu_irq_enable();
/* Initializing udc stack as HID composite device*/
udc_start();
sw_timer_get_id(&APP_TIMER);
/* Endless while loop */
while (1)
{
app_task(); /* Application task */
nwk_task(); /* RF4CE network layer task */
}
}
int main(void)
{
//! the page address to write to
uint8_t page_address;
//! the column address, or the X pixel.
uint8_t column_address;
//! store the LCD controller start draw line
uint8_t start_line_address = 0;
board_init();
sysclk_init();
// initialize the interface (SPI), ST7565R LCD controller and LCD
st7565r_init();
// set addresses at beginning of display
st7565r_set_page_address(0);
st7565r_set_column_address(0);
// fill display with lines
for (page_address = 0; page_address <= 4; page_address++) {
st7565r_set_page_address(page_address);
for (column_address = 0; column_address < 128; column_address++) {
st7565r_set_column_address(column_address);
/* fill every other pixel in the display. This will produce
horizontal lines on the display. */
st7565r_write_data(0xAA);
}
}
// scroll the display using hardware support in the LCD controller
while (true) {
st7565r_set_display_start_line_address(start_line_address++);
delay_ms(250);
}
}
int main (void)
{
/* Initialize the SAM system */
sysclk_init();
/* Initialize mcu's peripheral.*/
board_init();
/* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 );
/* Create freeRTOS START task.*/
xTaskCreate(task_start, (signed char *)"START", TASK_START_STACKSIZE, NULL,
TASK_START_PRIORITY, NULL);
/* Start the FreeRTOS + Trace record..*/
uiTraceStart();
/* Start the scheduler. */
vTaskStartScheduler();
// Insert application code here, after the board has been initialized.
return 0;
}
/*! \brief Main function. Execution starts here.
*/
int main(void)
{
irq_initialize_vectors();
cpu_irq_enable();
// Initialize the sleep manager
sleepmgr_init();
#if !SAM0
sysclk_init();
board_init();
#else
system_init();
#endif
ui_init();
// Start USB stack to authorize VBus monitoring
udc_start();
// The main loop manages only the power mode
// because the USB management is done by interrupt
while (true) {
sleepmgr_enter_sleep();
}
}
void *
initarm(struct arm_boot_params *abp)
{
struct pv_addr kernel_l1pt;
int loop;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t afterkern;
vm_offset_t lastaddr;
int i;
uint32_t memsize;
boothowto = 0; /* Likely not needed */
lastaddr = parse_boot_param(abp);
i = 0;
set_cpufuncs();
cpufuncs.cf_sleep = s3c24x0_sleep;
pcpu0_init();
/* Do basic tuning, hz etc */
init_param1();
#define KERNEL_TEXT_BASE (KERNBASE)
freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_va, (np)); \
(var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
#define alloc_pages(var, np) \
(var) = freemempos; \
freemempos += (np * PAGE_SIZE); \
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos += PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_va = freemempos -
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_pa =
kernel_pt_table[loop].pv_va - KERNVIRTADDR +
KERNPHYSADDR;
}
}
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
&kernel_pt_table[KERNEL_PT_SYS]);
for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
&kernel_pt_table[KERNEL_PT_KERN + i]);
pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
(((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the stack pages */
pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
}
arm_devmap_bootstrap(l1pagetable, s3c24x0_devmap);
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
set_stackptrs(0);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross reloations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/* Disable all peripheral interrupts */
ioreg_write32(S3C24X0_INTCTL_BASE + INTCTL_INTMSK, ~0);
memsize = board_init();
/* Find pclk for uart */
switch(ioreg_read32(S3C24X0_GPIO_BASE + GPIO_GSTATUS1) >> 16) {
case 0x3241:
s3c2410_clock_freq2(S3C24X0_CLKMAN_BASE, NULL, NULL,
&s3c2410_pclk);
break;
case 0x3244:
s3c2440_clock_freq2(S3C24X0_CLKMAN_BASE, NULL, NULL,
&s3c2410_pclk);
break;
}
cninit();
/* Set stack for exception handlers */
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
init_proc0(kernelstack.pv_va);
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1);
arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0]));
vm_max_kernel_address = KERNVIRTADDR + 3 * memsize;
pmap_bootstrap(freemempos, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
physmem = memsize / PAGE_SIZE;
phys_avail[0] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
phys_avail[1] = PHYSADDR + memsize;
phys_avail[2] = 0;
phys_avail[3] = 0;
init_param2(physmem);
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}
/**
* \brief Switch between various system clock sources and prescalers at
* run time.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
struct genclk_config gcfg;
sysclk_init();
board_init();
/* Setup SysTick Timer for 1 msec interrupts */
if (SysTick_Config(SystemCoreClock / 1000)) {
while (1); // Capture error
}
/* Enable PIO module related clock */
sysclk_enable_peripheral_clock(PIN_PUSHBUTTON_1_ID);
/* Configure specific CLKOUT pin */
ioport_set_pin_mode(GCLK_PIN, GCLK_PIN_MUX);
ioport_disable_pin(GCLK_PIN);
/* Configure the output clock source and frequency */
genclk_config_defaults(&gcfg, GCLK_ID);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_PLLACK);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1);
genclk_enable(&gcfg, GCLK_ID);
while (1) {
/*
* Initial state.
*/
wait_for_switches();
/*
* Divide MCK frequency by 2.
*/
sysclk_set_prescalers(SYSCLK_PRES_2);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_2);
genclk_enable(&gcfg, GCLK_ID);
wait_for_switches();
#ifdef BOARD_NO_32K_XTAL
/*
* Switch to the slow clock with all prescalers disabled.
*/
sysclk_set_source(SYSCLK_SRC_SLCK_RC);
sysclk_set_prescalers(SYSCLK_PRES_1);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_SLCK_RC);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1);
genclk_enable(&gcfg, GCLK_ID);
osc_disable(OSC_MAINCK_XTAL);
wait_for_switches();
#endif
/*
* Switch to internal 8 MHz RC.
*/
/* Switch to slow clock before switch main clock */
sysclk_set_source(SYSCLK_SRC_SLCK_RC);
osc_enable(OSC_MAINCK_8M_RC);
osc_wait_ready(OSC_MAINCK_8M_RC);
sysclk_set_source(SYSCLK_SRC_MAINCK_8M_RC);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_MAINCK_8M_RC);
genclk_enable(&gcfg, GCLK_ID);
wait_for_switches();
#if BOARD_FREQ_MAINCK_XTAL
/*
* Switch to external crystal (8MHz or 12MHz, depend on the board).
*/
osc_enable(OSC_MAINCK_XTAL);
osc_wait_ready(OSC_MAINCK_XTAL);
sysclk_set_source(SYSCLK_SRC_MAINCK_XTAL);
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_MAINCK_XTAL);
genclk_enable(&gcfg, GCLK_ID);
osc_disable(OSC_MAINCK_8M_RC);
wait_for_switches();
#endif
/*
* Go back to the initial state and start over.
*/
sysclk_init();
genclk_config_set_source(&gcfg, GENCLK_PCK_SRC_PLLACK);
genclk_config_set_divider(&gcfg, GENCLK_PCK_PRES_1);
genclk_enable(&gcfg, GCLK_ID);
}
}
/**
* \brief pio_capture Application entry point.
*
* \return Unused (ANSI-C compatibility).
*
*/
int main(void)
{
uint8_t uc_i;
uint32_t ul_length;
uint32_t ul_mode;
uint8_t uc_key;
static uint8_t uc_rx_even_only;
static uint8_t uc_tx_without_en;
/* Initialize the SAM system. */
sysclk_init();
board_init();
/* Configure UART for debug message output. */
configure_console();
/* Configure PIOA clock. */
pmc_enable_periph_clk(ID_PIOA);
pmc_enable_periph_clk(ID_PIOC);
/* Configure PIO Capture handler */
pio_capture_handler_set(capture_handler);
/* Output example information. */
puts(STRING_HEADER);
printf("Frequency: %d MHz.\r\n",
(uint8_t) (sysclk_get_cpu_hz() / 1000000));
printf("Press r to Receive data on PIO Parallel Capture.\r\n");
printf("Press s to Send data on PIO Parallel Capture.\r\n");
uc_key = 0;
while ((uc_key != 'r') && (uc_key != 's')) {
uart_read(CONSOLE_UART, &uc_key);
}
if (uc_key == 'r') {
printf("** RECEIVE mode **\r\n");
/* Initialize PIO capture mode value. */
ul_mode = 0;
/* Set up the parallel capture mode data size as 8 bits. */
ul_mode |= 0 << PIO_PCMR_DSIZE_Pos;
printf("Press y to sample the data when both data enable pins are enabled.\r\n");
printf("Press n to sample the data, don't care the status of the data enable pins.\r\n");
uc_key = 0;
while ((uc_key != 'y') && (uc_key != 'n')) {
uart_read(CONSOLE_UART, &uc_key);
}
if (uc_key == 'y') {
/* Sample the data when both data enable pins are enabled. */
ul_mode &= ~PIO_PCMR_ALWYS;
printf("Receive data when both data enable pins are enabled.\r\n");
} else {
/* Sample the data, don't care the status of the data enable pins. */
ul_mode |= PIO_PCMR_ALWYS;
printf("Receive data, don't care the status of the data enable pins.\r\n");
}
printf("Press y to sample all the data\r\n");
printf("Press n to sample the data only one out of two.\r\n");
uc_key = 0;
while ((uc_key != 'y') && (uc_key != 'n')) {
uart_read(CONSOLE_UART, &uc_key);
}
if (uc_key == 'y') {
/* Sample all the data. */
ul_mode &= ~PIO_PCMR_HALFS;
printf("All data are sampled.\r\n");
} else {
/* Sample the data only one out of two. */
ul_mode |= PIO_PCMR_HALFS;
/* Only if half-Sampling is set, data with an even index are sampled. */
ul_mode &= ~PIO_PCMR_FRSTS;
printf("Only one out of two data is sampled, with an even index.\r\n");
}
/* Initialize PIO Parallel Capture function. */
pio_capture_set_mode(PIOA, ul_mode);
pio_capture_enable(PIOA);
/* Disable all PIOA I/O line interrupt. */
pio_disable_interrupt(PIOA, 0xFFFFFFFF);
/* Configure and enable interrupt of PIO. */
NVIC_DisableIRQ(PIOA_IRQn);
NVIC_ClearPendingIRQ(PIOA_IRQn);
NVIC_SetPriority(PIOA_IRQn, PIO_IRQ_PRI);
NVIC_EnableIRQ(PIOA_IRQn);
while (1) {
g_uc_cbk_received = 0;
/* Clear Receive buffer. */
for (uc_i = 0; uc_i < SIZE_BUFF_RECEPT; uc_i++) {
pio_rx_buffer[uc_i] = 0;
}
/* Set up PDC receive buffer, waiting for 64 bytes. */
packet_t.ul_addr = (uint32_t) pio_rx_buffer;
packet_t.ul_size = SIZE_BUFF_RECEPT;
p_pdc = pio_capture_get_pdc_base(PIOA);
pdc_rx_init(p_pdc, &packet_t, NULL);
/* Enable PDC transfer. */
pdc_enable_transfer(p_pdc, PERIPH_PTCR_RXTEN);
/* Configure the PIO capture interrupt mask. */
pio_capture_enable_interrupt(PIOA,
(PIO_PCIER_ENDRX | PIO_PCIER_RXBUFF));
printf("Waiting...\r\n");
while (g_uc_cbk_received == 0) {
}
}
} else if (uc_key == 's') {
printf("** SEND mode **\r\n");
printf("This is for debug purpose only !\r\n");
printf("Frequency of PIO controller clock must be strictly superior");
printf("to 2 times the frequency of the clock of the device which");
printf(" generates the parallel data.\r\n");
printf("\r\nPlease connect the second board, ");
printf("and put it in receive mode.\r\n");
/* Configure PIO pins which simulate as a sensor. */
pio_configure_pin_group(PIOA, PIO_CAPTURE_CONTROL_PIN_MSK,
PIO_CAPTURE_OUTPUT_PIN_FLAGS);
pio_configure_pin_group(PIOC, PIO_CAPTURE_DATA_PINS_MASK,
PIO_CAPTURE_OUTPUT_PIN_FLAGS);
pio_set_pin_low(PIO_CAPTURE_EN1_IDX);
pio_set_pin_low(PIO_CAPTURE_EN2_IDX);
pio_set_pin_low(PIO_CAPTURE_CCLK_IDX);
/* Enable sync. output data. */
pio_enable_output_write(PIOC, PIO_CAPTURE_DATA_PINS_MASK);
/* Initialize the capture data line. */
pio_sync_output_write(PIOC, 0);
printf("Press y to send data with data enable pins.\r\n");
printf("Press n to send data without data enable pins.\r\n");
uc_key = 0;
while ((uc_key != 'y') && (uc_key != 'n')) {
uart_read(CONSOLE_UART, &uc_key);
}
if (uc_key == 'y') {
uc_tx_without_en = 0;
printf("Send data with both data enable pins enabled.\r\n");
} else {
uc_tx_without_en = 1;
printf("Send data without enabling the data enable pins.\r\n");
}
printf("Press y to indicate that receiver samples all data.\r\n");
printf("Press n to indicate that receiver samples data with an even index.\r\n");
uc_key = 0;
while ((uc_key != 'y') && (uc_key != 'n')) {
uart_read(CONSOLE_UART, &uc_key);
}
if (uc_key == 'y') {
uc_rx_even_only = 0;
printf("Receiver samples all data.\r\n");
} else {
uc_rx_even_only = 1;
printf("Receiver samples data with an even index.\r\n");
}
ul_length = SIZE_BUFF_RECEPT * (1 + uc_rx_even_only);
while (1) {
if (uc_tx_without_en) {
printf("\r\nSend data without enabling the data enable pins.\r\n");
} else {
printf("\r\nSend data with both data enable pins enabled.\r\n");
}
if (!uc_tx_without_en) {
/* Set enable pins. */
pio_set_pin_high(PIO_CAPTURE_EN1_IDX);
pio_set_pin_high(PIO_CAPTURE_EN2_IDX);
}
for (uc_i = 0; uc_i < ul_length;) {
/* Send data. */
pio_sync_output_write(PIOC,
(uc_i << PIO_CAPTURE_DATA_POS));
/* Set clock. */
pio_set_pin_high(PIO_CAPTURE_CCLK_IDX);
delay_us(20);
/* Clear clock. */
pio_set_pin_low(PIO_CAPTURE_CCLK_IDX);
delay_us(20);
uc_i++;
}
if (!uc_tx_without_en) {
/* Clear enable pins. */
pio_set_pin_low(PIO_CAPTURE_EN1_IDX);
pio_set_pin_low(PIO_CAPTURE_EN2_IDX);
}
printf("Press a key.\r\n");
while (uart_read(CONSOLE_UART, &uc_key)) {
}
}
}
return 0;
}
void board_init_r(gd_t *id, ulong dest_addr)
{
ulong malloc_start;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
/*
* TODO: printing of the clock inforamtion of the board is now
* implemented as part of bdinfo command. Currently only support for
* davinci SOC's is added. Remove this check once all the board
* implement this.
*/
#ifdef CONFIG_CLOCKS
set_cpu_clk_info(); /* Setup clock information */
#endif
serial_initialize();
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r();
#endif
power_init_board();
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#if defined(CONFIG_CMD_NAND)
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_CMD_SCSI
puts("SCSI: ");
scsi_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
if (should_load_env())
env_relocate();
else
set_default_env(NULL);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
# ifdef CONFIG_OF_CONTROL
/* Put this here so it appears on the LCD, now it is ready */
display_fdt_model(gd->fdt_blob);
# else
checkboard();
# endif
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
#ifdef CONFIG_FASTBOOT
fastboot_setup();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
puts("Net: ");
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram = 0;
uchar memsz[32];
#ifdef CONFIG_PRAM
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
#ifdef CONFIG_FASTBOOT
check_fastboot();
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
/**
\brief The program starts executing here.
*/
int mote_main(void) {
uint8_t i;
// clear local variables
memset(&app_vars,0,sizeof(app_vars_t));
// initialize board
board_init();
GPIO_Configuration();
EXTI_Configuration();
GPIOD->BRR = (uint32_t)GPIO_Pin_2;
#ifdef RADIO_SLEEP
PORT_PIN_RADIO_SLP_TR_CNTL_HIGH();
#ifdef RADIO_SLEEP_IN_RUN_MOdE
while(1);
#endif
board_sleep();
#endif
#ifdef RADIO_TRXOFF
board_sleep();
#endif
// add callback functions radio
radio_setOverflowCb(cb_radioTimerOverflows);
radio_setCompareCb(cb_radioTimerCompare);
radio_setStartFrameCb(cb_startFrame);
radio_setEndFrameCb(cb_endFrame);
// prepare packet
app_vars.packet_len = sizeof(app_vars.packet);
for (i=0;i<app_vars.packet_len;i++) {
app_vars.packet[i] = ID;
}
// start bsp timer
bsp_timer_set_callback(cb_timer);
bsp_timer_scheduleIn(TIMER_PERIOD);
// prepare radio
radio_rfOn();
radio_setFrequency(CHANNEL);
// switch in RX by default
radio_rxEnable();
app_vars.state = APP_STATE_RX;
#ifdef RADIO_RX_ON
leds_all_off();
board_sleep();
#endif
// start by a transmit
app_vars.flags |= APP_FLAG_TIMER;
while (1) {
// sleep while waiting for at least one of the flags to be set
while (app_vars.flags==0x00) {
board_sleep();
}
// handle and clear every flag
while (app_vars.flags) {
if (app_vars.flags & APP_FLAG_START_FRAME) {
// start of frame
switch (app_vars.state) {
case APP_STATE_RX:
// started receiving a packet
leds_error_on();
break;
case APP_STATE_TX:
// started sending a packet
leds_sync_on();
break;
}
// clear flag
app_vars.flags &= ~APP_FLAG_START_FRAME;
}
if (app_vars.flags & APP_FLAG_END_FRAME) {
// end of frame
switch (app_vars.state) {
case APP_STATE_RX:
// done receiving a packet
app_vars.packet_len = sizeof(app_vars.packet);
for (i=0;i<app_vars.packet_len;i++) {
app_vars.packet[i] = 0;
}
// get packet from radio
radio_getReceivedFrame(app_vars.packet,
&app_vars.packet_len,
sizeof(app_vars.packet),
&app_vars.rxpk_rssi,
&app_vars.rxpk_lqi,
&app_vars.rxpk_crc);
leds_error_off();
break;
case APP_STATE_TX:
// done sending a packet
// switch to RX mode
radio_rxEnable();
app_vars.state = APP_STATE_RX;
leds_sync_off();
break;
}
// clear flag
app_vars.flags &= ~APP_FLAG_END_FRAME;
}
if (app_vars.flags & APP_FLAG_TIMER) {
// timer fired
if (app_vars.state==APP_STATE_RX) {
// stop listening
radio_rfOff();
// prepare packet
app_vars.packet_len = sizeof(app_vars.packet);
for (i=0;i<app_vars.packet_len;i++) {
app_vars.packet[i] = ID;
}
// start transmitting packet
radio_loadPacket(app_vars.packet,app_vars.packet_len);
radio_txEnable();
#ifdef RADIO_PLL_ON
leds_all_off();
board_sleep();
#endif
radio_txNow();
#ifdef RADIO_BUSY_TX
leds_all_off();
while(1) { //keep sending
PORT_PIN_RADIO_SLP_TR_CNTL_HIGH();
PORT_PIN_RADIO_SLP_TR_CNTL_LOW();
}
board_sleep();
#endif
app_vars.state = APP_STATE_TX;
}
// clear flag
app_vars.flags &= ~APP_FLAG_TIMER;
}
}
}
}
/**
* \brief Application entry point for AT25DFx example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
uint16_t i;
sysclk_init();
board_init();
/* Initialize the SerialFlash */
at25dfx_initialize();
/* Set the SerialFlash active */
at25dfx_set_mem_active(AT25DFX_MEM_ID);
/* Unprotect the chip */
if (at25dfx_protect_chip(AT25_TYPE_UNPROTECT) == AT25_SUCCESS) {
LED_On(DATA_FLASH_LED_EXAMPLE_0);
} else {
test_ko();
}
/* Check if the SerialFlash is valid */
if (at25dfx_mem_check() == AT25_SUCCESS) {
LED_On(DATA_FLASH_LED_EXAMPLE_0);
} else {
test_ko();
}
/* Prepare half of the SerialFlash sector as 0xAA */
for (i = 0; i < AT25DFX_TEST_DATA_SIZE / 2; i++) {
ram_buff[i] = 0xAA;
}
/* And the remaining half as 0x55 */
for (; i < AT25DFX_TEST_DATA_SIZE; i++) {
ram_buff[i] = 0x55;
}
/* Erase the block before write */
at25dfx_erase_block(AT25DFX_TEST_BLOCK_ADDR);
/* Write the data to the SerialFlash */
at25dfx_write(ram_buff, AT25DFX_TEST_DATA_SIZE, AT25DFX_TEST_BLOCK_ADDR);
/* Read back this sector and compare them with the expected values */
at25dfx_read(ram_buff, AT25DFX_TEST_DATA_SIZE, AT25DFX_TEST_BLOCK_ADDR);
for (i = 0; i < AT25DFX_TEST_DATA_SIZE / 2; i++) {
if (ram_buff[i] != 0xAA) {
test_ko();
}
}
for (; i < AT25DFX_TEST_DATA_SIZE; i++) {
if (ram_buff[i] != 0x55) {
test_ko();
}
}
/* Write one SerialFlash sector as 0x00, 0x01 .... */
for (i = 0; i < AT25DFX_TEST_DATA_SIZE; i++) {
ram_buff[i] = i;
}
/* Erase the block before write */
at25dfx_erase_block(AT25DFX_TEST_BLOCK_ADDR);
/* Write the data to the SerialFlash */
at25dfx_write(ram_buff, AT25DFX_TEST_DATA_SIZE, AT25DFX_TEST_BLOCK_ADDR);
/* Read back this sector and compare them with the expected values */
at25dfx_read(ram_buff, AT25DFX_TEST_DATA_SIZE, AT25DFX_TEST_BLOCK_ADDR);
for (i = 0; i < AT25DFX_TEST_DATA_SIZE; i++) {
if (ram_buff[i] != (i % 0x100)) {
test_ko();
}
}
LED_On(DATA_FLASH_LED_EXAMPLE_1);
while (1);
}
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS,
};
char binary[16 + 1];
uint8_t i;
bool oversampling_is_enabled;
/* Usual initializations */
board_init();
sysclk_init();
sleepmgr_init();
irq_initialize_vectors();
cpu_irq_enable();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
printf("\x0C\n\r-- ADC Over-sampling Example --\n\r");
printf("-- Compiled: %s %s --\n\r\n\r", __DATE__, __TIME__);
printf("Commands:\n\r");
printf("- key 'o' to enable over-sampling\n\r");
printf("- key 'd' to disable over-sampling\n\r");
/* ADC initializations */
main_adc_init();
main_adc_oversampling_stop();
oversampling_is_enabled = false;
while (1) {
if (usart_rx_is_complete(CONF_TEST_USART)) {
char key = getchar();
if (key == 'o') {
main_adc_oversampling_start();
oversampling_is_enabled = true;
}
if (key == 'd') {
main_adc_oversampling_stop();
oversampling_is_enabled = false;
}
}
/* Wait sample with or without over-sampling */
uint16_t sample;
adc_wait_for_interrupt_flag(&ADCA, ADC_CH0);
sample = adc_get_unsigned_result(&ADCA, ADC_CH0);
if (!oversampling_is_enabled) {
sample <<= 4;
}
i = 15;
do {
binary[i] = '0' + (sample & 1);
sample >>= 1;
} while (i--);
binary[16] = 0;
printf("ADC Value: %sb\r", binary);
}
}
/**
* Initialize the PDCA transfer for the example.
*/
static void init_pdca(void)
{
/* PDCA channel options */
static const pdca_channel_config_t pdca_tx_configs = {
.addr = (void *)event_string,
.pid = PDCA_PID_USART2_TX,
.size = sizeof(event_string),
.r_addr = 0,
.r_size = 0,
.ring = false,
.etrig = true,
.transfer_size = PDCA_MR_SIZE_BYTE
};
/* Enable PDCA module */
pdca_enable(PDCA);
/* Init PDCA channel with the pdca_options.*/
pdca_channel_set_config(PEVC_ID_USER_PDCA_0, &pdca_tx_configs);
/* Set callback for PDCA channel */
pdca_channel_set_callback(PEVC_ID_USER_PDCA_0, pdca_tranfer_done,
PDCA_0_IRQn, 1, PDCA_IER_TRC | PDCA_IER_TERR);
/* Enable PDCA channel */
pdca_channel_enable(PEVC_ID_USER_PDCA_0);
}
/**
* Configure serial console.
*/
static void configure_console(void)
{
const usart_serial_options_t uart_serial_options = {
.baudrate = CONF_UART_BAUDRATE,
#ifdef CONF_UART_CHAR_LENGTH
.charlength = CONF_UART_CHAR_LENGTH,
#endif
.paritytype = CONF_UART_PARITY,
#ifdef CONF_UART_STOP_BITS
.stopbits = CONF_UART_STOP_BITS,
#endif
};
/* Configure console. */
stdio_serial_init(CONF_UART, &uart_serial_options);
}
/**
* \brief Main entry point for event example.
*/
int main(void)
{
/* Initialize the SAM system */
sysclk_init();
board_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
printf("\r\n\r\n-- Events example 2 --\r\n");
printf("-- %s\r\n", BOARD_NAME);
printf("-- Compiled: %s %s --\r\n", __DATE__, __TIME__);
/* Configure pin to trigger an enent on falling edge */
ioport_set_pin_mode(CONF_EXAMPLE_PIN_EVENT, IOPORT_MODE_PULLUP |
IOPORT_MODE_MUX_C);
ioport_disable_pin(CONF_EXAMPLE_PIN_EVENT);
ioport_set_pin_sense_mode(CONF_EXAMPLE_PIN_EVENT, IOPORT_SENSE_FALLING);
gpio_enable_pin_periph_event(CONF_EXAMPLE_PIN_EVENT);
printf(CONF_EXAMPLE_EVENT_MSG);
init_events();
init_pdca();
while (1) {
/* Toggle LED0 every 500 ms */
LED_Toggle(LED0);
delay_ms(500);
}
}
/**
\brief The program starts executing here.
*/
int mote_main(void) {
// clear local variables
memset(&app_vars,0,sizeof(app_vars_t));
// initialize board
board_init();
// add callback functions radio
radio_setOverflowCb(cb_radioTimerOverflows);
radio_setCompareCb(cb_radioTimerCompare);
radio_setStartFrameCb(cb_startFrame);
radio_setEndFrameCb(cb_endFrame);
// setup UART
uart_setCallbacks(cb_uartTxDone,cb_uartRxCb);
// prepare radio
radio_rfOn();
radio_setFrequency(CHANNEL);
// switch in RX
radio_rxEnable();
while (1) {
// sleep while waiting for at least one of the rxpk_done to be set
app_vars.rxpk_done = 0;
while (app_vars.rxpk_done==0) {
board_sleep();
}
// if I get here, I just received a packet
//===== get packet from radio
// led
leds_sync_on();
// get packet from radio
radio_getReceivedFrame(
app_vars.rxpk_buf,
&app_vars.rxpk_len,
sizeof(app_vars.rxpk_buf),
&app_vars.rxpk_rssi,
&app_vars.rxpk_lqi,
&app_vars.rxpk_crc
);
// read the packet number
app_vars.rxpk_num = app_vars.rxpk_buf[0];
// led
leds_sync_off();
//===== send notification over serial port
// led
leds_error_on();
// format frame to send over serial port
app_vars.uart_txFrame[0] = app_vars.rxpk_len; // packet length
app_vars.uart_txFrame[1] = app_vars.rxpk_num; // packet number
app_vars.uart_txFrame[2] = app_vars.rxpk_rssi; // RSSI
app_vars.uart_txFrame[3] = app_vars.rxpk_lqi; // LQI
app_vars.uart_txFrame[4] = app_vars.rxpk_crc; // CRC
app_vars.uart_txFrame[5] = 0xff; // closing flag
app_vars.uart_txFrame[6] = 0xff; // closing flag
app_vars.uart_txFrame[7] = 0xff; // closing flag
app_vars.uart_done = 0;
app_vars.uart_lastTxByte = 0;
// send app_vars.uart_txFrame over UART
uart_clearTxInterrupts();
uart_clearRxInterrupts();
uart_enableInterrupts();
uart_writeByte(app_vars.uart_txFrame[app_vars.uart_lastTxByte]);
while (app_vars.uart_done==0); // busy wait to finish
uart_disableInterrupts();
// led
leds_error_off();
}
}
int main (void)
{
/* Insert system clock initialization code here (sysclk_init()). */
sysclk_init();
board_init();
/* Insert application code here, after the board has been initialized. */
if (SysTick_Config(sysclk_get_cpu_hz() / 1000)) {
puts("-E- Systick configuration error\r");
while (1) {
/* Capture error */
gpio_set_pin_low(LED2_GPIO);
}
}
config_lcd();
pmc_enable_periph_clk(ID_ENC);
//Interrupt for A:
pio_set_input(PIOA, GPIO_A, PIO_DEFAULT);
pio_pull_down(PIOA, GPIO_A, ENABLE);
pio_handler_set(PIOA, ID_ENC, GPIO_A, PIO_IT_RISE_EDGE, pin_handler);
pio_enable_interrupt(PIOA, GPIO_A);
//Interrupt for B:
pio_set_input(PIOA, GPIO_B, PIO_DEFAULT);
pio_pull_down(PIOA, GPIO_B, ENABLE);
pio_handler_set(PIOA, ID_ENC, GPIO_B, PIO_IT_RISE_EDGE, pin_handler);
pio_enable_interrupt(PIOA, GPIO_B);
//Interrupt for C:
pio_set_input(PIOA, GPIO_C, PIO_DEFAULT);
pio_pull_down(PIOA, GPIO_C, ENABLE);
//pio_handler_set(PIOA, ID_ENC, GPIO_C, PIO_IT_RISE_EDGE, pin_handler);
pio_handler_set(PIOA, ID_ENC, GPIO_C, PIO_IT_FALL_EDGE, pin_handler);
pio_enable_interrupt(PIOA, GPIO_C);
//Enable Interrupt GPIO:
NVIC_DisableIRQ(PIOA_IRQn);
NVIC_ClearPendingIRQ(PIOA_IRQn);
NVIC_SetPriority(PIOA_IRQn, 0);
NVIC_EnableIRQ(PIOA_IRQn);
ili9225_set_foreground_color(COLOR_BLACK);
ili9225_draw_string(10,10, (uint8_t *)"Encoder Test");
while (1){
ili9225_set_foreground_color(COLOR_WHITE);
ili9225_draw_filled_rectangle(0,30,ILI9225_LCD_WIDTH,ILI9225_LCD_HEIGHT);
ili9225_set_foreground_color(COLOR_BLACK);
graus = ((float)round/ENC_RES)*VOLTA_COMP;
snprintf(buf, sizeof(buf), "Graus:%.3f", graus );
ili9225_draw_string(10,50, buf);
snprintf(buf, sizeof(buf), "Round:%d", round );
ili9225_draw_string(10,80, buf);
mdelay(500);
}
}
int main( void )
{
int keysize;
unsigned long i, j, tsc;
unsigned char tmp[64];
t_cpu_time timer;
/* Keep compiler happy */
UNUSED(keysize);
UNUSED(i);
UNUSED(j);
UNUSED(tsc);
UNUSED(tmp[0]);
UNUSED(timer);
// USART options.
static usart_serial_options_t USART_SERIAL_OPTIONS =
{
.baudrate = USART_SERIAL_EXAMPLE_BAUDRATE,
.charlength = USART_SERIAL_CHAR_LENGTH,
.paritytype = USART_SERIAL_PARITY,
.stopbits = USART_SERIAL_STOP_BIT
};
sysclk_init();
// Initialize the board.
// The board-specific conf_board.h file contains the configuration of the board
// initialization.
board_init();
// Initialize Serial Interface using Stdio Library
stdio_serial_init(USART_SERIAL_EXAMPLE,&USART_SERIAL_OPTIONS);
printf( "Start Benchmark\n");
#if defined(POLARSSL_ARC4_C)
arc4_context arc4;
#endif
#if defined(POLARSSL_DES_C)
des3_context des3;
des_context des;
#endif
#if defined(POLARSSL_AES_C)
aes_context aes;
#endif
#if defined(POLARSSL_CAMELLIA_C)
camellia_context camellia;
#endif
#if defined(POLARSSL_RSA_C)
rsa_context rsa;
#endif
memset( buf, 0xAA, sizeof( buf ) );
printf( "\n" );
#if defined(POLARSSL_MD4_C)
printf( " MD4 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
md4( buf, BUFSIZE, tmp );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
md4( buf, BUFSIZE, tmp );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_MD5_C)
printf( " MD5 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
md5( buf, BUFSIZE, tmp );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
md5( buf, BUFSIZE, tmp );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_SHA1_C)
printf( " SHA-1 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
sha1( buf, BUFSIZE, tmp );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
sha1( buf, BUFSIZE, tmp );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_SHA2_C)
printf( " SHA-256 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
sha2( buf, BUFSIZE, tmp, 0 );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
sha2( buf, BUFSIZE, tmp, 0 );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_SHA4_C)
printf( " SHA-512 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
sha4( buf, BUFSIZE, tmp, 0 );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
sha4( buf, BUFSIZE, tmp, 0 );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_ARC4_C)
printf( " ARC4 : " );
fflush( stdout );
arc4_setup( &arc4, tmp, 32 );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
arc4_crypt( &arc4, BUFSIZE, buf, buf );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
arc4_crypt( &arc4, BUFSIZE, buf, buf );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_DES_C)
printf( " 3DES : " );
fflush( stdout );
des3_set3key_enc( &des3, tmp );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
des3_crypt_cbc( &des3, DES_ENCRYPT, BUFSIZE, tmp, buf, buf );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
des3_crypt_cbc( &des3, DES_ENCRYPT, BUFSIZE, tmp, buf, buf );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
printf( " DES : " );
fflush( stdout );
des_setkey_enc( &des, tmp );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
des_crypt_cbc( &des, DES_ENCRYPT, BUFSIZE, tmp, buf, buf );
tsc = hardclock();
for( j = 0; j < 1024; j++ )
des_crypt_cbc( &des, DES_ENCRYPT, BUFSIZE, tmp, buf, buf );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
#endif
#if defined(POLARSSL_AES_C)
for( keysize = 128; keysize <= 256; keysize += 64 )
{
printf( " AES-%d : ", keysize );
fflush( stdout );
memset( buf, 0, sizeof( buf ) );
memset( tmp, 0, sizeof( tmp ) );
aes_setkey_enc( &aes, tmp, keysize );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
aes_crypt_cbc( &aes, AES_ENCRYPT, BUFSIZE, tmp, buf, buf );
tsc = hardclock();
for( j = 0; j < 4096; j++ )
aes_crypt_cbc( &aes, AES_ENCRYPT, BUFSIZE, tmp, buf, buf );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
}
#endif
#if defined(POLARSSL_CAMELLIA_C)
for( keysize = 128; keysize <= 256; keysize += 64 )
{
printf( " CAMELLIA-%d : ", keysize );
fflush( stdout );
memset( buf, 0, sizeof( buf ) );
memset( tmp, 0, sizeof( tmp ) );
camellia_setkey_enc( &camellia, tmp, keysize );
cpu_set_timeout(cpu_ms_2_cy(1000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
camellia_crypt_cbc( &camellia, CAMELLIA_ENCRYPT, BUFSIZE, tmp, buf, buf );
tsc = hardclock();
for( j = 0; j < 4096; j++ )
camellia_crypt_cbc( &camellia, CAMELLIA_ENCRYPT, BUFSIZE, tmp, buf, buf );
printf( "%9lu Kb/s, %9lu cycles/byte\n", i * BUFSIZE / 1024,
( hardclock() - tsc ) / ( j * BUFSIZE ) );
}
#endif
#if defined(POLARSSL_RSA_C)
rsa_init( &rsa, RSA_PKCS_V15, 0 );
rsa_gen_key( &rsa, myrand, NULL, 1024, 65537 );
printf( " RSA-1024 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(3000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
{
buf[0] = 0;
rsa_public( &rsa, buf, buf );
}
printf( "%9lu public/s\n", i / 3 );
printf( " RSA-1024 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(3000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
{
buf[0] = 0;
rsa_private( &rsa, buf, buf );
}
printf( "%9lu private/s\n", i / 3 );
rsa_free( &rsa );
rsa_init( &rsa, RSA_PKCS_V15, 0 );
rsa_gen_key( &rsa, myrand, NULL, 2048, 65537 );
printf( " RSA-2048 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(3000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
{
buf[0] = 0;
rsa_public( &rsa, buf, buf );
}
printf( "%9lu public/s\n", i / 3 );
printf( " RSA-2048 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(3000, CPU_HZ),&timer);
for( i = 1; ! cpu_is_timeout(&timer); i++ )
{
buf[0] = 0;
rsa_private( &rsa, buf, buf );
}
printf( "%9lu private/s\n", i / 3 );
rsa_free( &rsa );
rsa_init( &rsa, RSA_PKCS_V15, 0 );
rsa_gen_key( &rsa, myrand, NULL, 4096, 65537 );
printf( " RSA-4096 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(3000, CPU_HZ),&timer);
for( i = 1; !cpu_is_timeout(&timer); i++ )
{
buf[0] = 0;
rsa_public( &rsa, buf, buf );
}
printf( "%9lu public/s\n", i / 3 );
printf( " RSA-4096 : " );
fflush( stdout );
cpu_set_timeout(cpu_ms_2_cy(3000, CPU_HZ),&timer);
for( i = 1; ! cpu_is_timeout(&timer); i++ )
{
buf[0] = 0;
rsa_private( &rsa, buf, buf );
}
printf( "%9lu private/s\n", i / 3 );
rsa_free( &rsa );
#endif
printf( "\n" );
#ifdef WIN32
printf( " Press Enter to exit this program.\n" );
fflush( stdout ); getchar();
#endif
return( 0 );
}
int main(void)
{
struct dac_config conf;
uint8_t i = 0;
board_init();
sysclk_init();
// Initialize the dac configuration.
dac_read_configuration(&SPEAKER_DAC, &conf);
/* Create configuration:
* - 1V from bandgap as reference, left adjusted channel value
* - one active DAC channel, no internal output
* - conversions triggered by event channel 0
* - 1 us conversion intervals
*/
dac_set_conversion_parameters(&conf, DAC_REF_BANDGAP, DAC_ADJ_LEFT);
dac_set_active_channel(&conf, SPEAKER_DAC_CHANNEL, 0);
dac_set_conversion_trigger(&conf, SPEAKER_DAC_CHANNEL, 0);
#if XMEGA_DAC_VERSION_1
dac_set_conversion_interval(&conf, 1);
#endif
dac_write_configuration(&SPEAKER_DAC, &conf);
dac_enable(&SPEAKER_DAC);
#if XMEGA_E
// Configure timer/counter to generate events at sample rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC4);
TCC4.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC4_OVF_gc;
// Start the timer/counter.
TCC4.CTRLA = TC45_CLKSEL_DIV1_gc;
#else
// Configure timer/counter to generate events at sample rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC0);
TCC0.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC0_OVF_gc;
// Start the timer/counter.
TCC0.CTRLA = TC_CLKSEL_DIV1_gc;
#endif
/* Write samples to the DAC channel every time it is ready for new
* data, i.e., when it is done converting. Conversions are triggered by
* the timer/counter.
*/
do {
dac_wait_for_channel_ready(&SPEAKER_DAC, SPEAKER_DAC_CHANNEL);
dac_set_channel_value(&SPEAKER_DAC, SPEAKER_DAC_CHANNEL, sine[i]);
i++;
i %= NR_OF_SAMPLES;
} while (1);
}
/**
* Starts the initialization, the tasks and then the scheduler.
*/
int main(void)
{
/* disable ETM at very first */
PINSEL10 &= ~((unsigned int)(1 << 3));
/* Initialize BMC hardware */
global_data.bmc_resetcause = 0x00;
/* IPMI message sequence counter */
global_data.seq_counter = 0x00;
/* site number used for entity instance */
global_data.bmc_siteno = 0x00;
/* reset sdr list */
sdr_list.sdr_count = 0;
/* init PLL */
init_clock();
/* init interrupts */
init_irq();
/* get reset cause */
init_resetcause();
/* init port pins */
init_portpins();
/* CUSTOM BOARD INIT CODE LOCATION 1 */
custom_init_1();
/* get HW and IPMB address */
custom_get_hw_ipmb_address();
uptime_init();
/* init RTC */
rtc_init();
/* create the FreeRTOS queues */
create_queues();
uart_init(UART_DEBUG_CONNECTOR, 115200);
uart_printf("Firmware started...\n");
/* init SPI/SSP controllers */
spi_init();
/* init SPI FLASH */
spi_flash_init_devices();
spi_flash_init(&spi_flash);
#ifdef CFG_MMC_I2C_MASTER
/* init BMC master I2C bus */
master_i2c_init(MASTER_BUS_I2C);
#endif
/* init EEPROM file system */
//spi_eeprom_init(&spi_eeprom);
#ifdef CFG_FS
if (fs_init(&efs, &spi_eeprom) != 0)
{
uart_printf("\nEEPROM not accesable!\n");
/* reboot bmc */
lpc_watchdog_start(CFG_BL_WATCHDOG_TIMEOUT, WD_RESET_MODE);
while (1);
}
#endif
/* init leds */
//led_init();
#ifndef CFG_ONCHIP_FLASH_GLOBAL_CONF
/* check EEPROM areas */
//eeprom_integrity_check_areas();
#endif
/* init CLI (and debug console) */
cli_uart_init(115200);
/* handle reset type warm/cold? */
//fru_handle_reset_type();
#ifdef CFG_CM
cm_fru_get_last_known_state();
#endif
#ifdef CFG_EXT_INT
/* init external interrupts */
external_interrupt_init();
#endif
#ifdef CFG_HELPER
/* init the helper task */
helper_init();
#endif
#ifdef CFG_BIOS_FLASH
/* init BIOS FLASH */
spi_flash_init(&bios_flash);
/* init FPGA BIOS flash selection */
bios_restore_active_flash_from_eeprom();
#endif
/* CUSTOM BOARD INIT CODE LOCATION 2 */
//custom_init_2();
/* get global configuration from EEPROM */
global_config();
/* CUSTOM BOARD INIT CODE LOCATION 3 */
//custom_init_3();
/* parse FRU */
fru_init(0);
#if defined (CFG_CM) || defined (CFG_MMC) || defined (CFG_IRTM) || defined(CFG_MCMC)
/* init the IPMB-L interface(s) */
ipmbl_init();
#endif
#ifdef CFG_LAN
/* read and set ncsi mac address from fru */
custom_set_ncsi_mac();
#endif
/* create message pool for IPMI messages */
message_pool_init();
/* init board task */
board_init();
/* init the BMC task */
bmc_init();
#ifdef CFG_PI_SERIAL_BASIC
/* init the payload interface */
pi_uart_b_init(CFG_PI_PORT_RATE);
#endif /* CFG_PI_SERIAL_BASIC */
#ifdef CFG_PI_SERIAL_TERMINAL
/* init the payload interface */
pi_uart_t_init(CFG_PI_PORT_RATE);
#endif /* CFG_PI_SERIAL_TERMINAL */
#ifdef CFG_PI_KCS
/* initialise kcs interface */
kcs_init();
#endif /* CFG_PI_KCS */
#ifdef CFG_ATCA
if (global_conf.operation_mode == OPERATION_MODE_STANDALONE)
{
/* configure IPMB-A and IPMB-B as master only in stanalone mode */
master_i2c_init(IPMB0A_I2C);
master_i2c_init(IPMB0B_I2C);
/* enable IPMB-0 pull ups and buffer */
ipmb0_bus_ctrl(IPMB0_A, IPMB_ENABLE);
ipmb0_bus_ctrl(IPMB0_B, IPMB_ENABLE);
}
else
{
/* init the IPMB-0 interface */
ipmb0_init();
}
#endif
#ifdef CFG_LAN_PLUS
sol_init();
#endif
#ifdef CFG_LAN
/* init ethernet hardware and Task */
eth_start();
#endif
/* init the SDR task */
/* PORT_NOTE: Needs to be started AFTER BMC task because of Semaphore dependency */
sdr_init();
/* parse all PICMG Records in FRU data and store relevant information */
//fru_parse_picmg();
/* init the IPMI message hub */
msg_hub_init();
/* init the event task */
event_init();
#ifdef CFG_CM
/* init the CM task */
init_cm();
#endif
#ifdef CFG_COOLING_MANAGER
cool_init();
#endif
/* do all post tests */
//post_test();
/* needs to be done after sdr initialization */
//hpm_check_bl_flags();
#ifdef CFG_BIOS_FLASH
/* collect BIOS/NVRAM version info (if payload power is off) */
if (!(signal_read(&sig_payload_power_enable)))
{
bios_redundancy_get_versions();
}
#endif
#ifdef CFG_WATCHDOG
/* start the FW watchdog */
lpc_watchdog_start(CFG_FW_WATCHDOG_TIMEOUT, WD_RESET_MODE);
#endif
/* set desired debug output mode before starting scheduler */
global_debug_uart_enabled = CFG_GLOBAL_DEBUG_UART;
/* all tasks have been initialized, start the scheduler */
vTaskStartScheduler();
/* Should never reach here! */
while (1);
}
/** \brief This function is the entry function for an example application that
uses the SHA204 ASF component.
* \return result (0: success, otherwise failure)
*/
int main(void)
{
static uint8_t tx_buffer_command[CHECKMAC_COUNT]; // biggest command in this example
static uint8_t rx_buffer[SHA204_RSP_SIZE_MAX];
static uint8_t challenge[MAC_CHALLENGE_SIZE];
static uint8_t other_data[CHECKMAC_OTHER_DATA_SIZE];
uint8_t sha204_lib_return = SHA204_SUCCESS;
uint32_t loop_count = 0;
uint8_t i2c_address_index = 0;
uint8_t twi_address_client;
uint8_t twi_address_host;
// Initialize system clock.
sysclk_init();
// Initialize board.
board_init();
// Initialize logging (USART).
log_init();
// Initialize interrupt vectors.
irq_initialize_vectors();
// Send example info.
log_sha204_title("ATSHA204 Mac / CheckMac Example\r\n");
// Indicate entering main loop.
led_display_number(0xFF);
sha204h_delay_ms(1000);
// The main loop wakes up all four devices, sends a Mac command to one serving
// as a client, and subsequently a CheckMac command with the Mac challenge and response data
// to another SHA204 serving as a host. At the end of the loop, all four devices
// are put back to sleep by sending a Sleep command to every one of them.
while (true) {
// Indicate success or error for some time.
led_display_number(sha204_lib_return);
sha204h_delay_ms(1000);
log_sha204_title("----------------------");
sprintf((char *) tx_buffer_command, "loop count = %lu", loop_count++);
log_sha204_title((char *) tx_buffer_command);
// Indicate that Mac / CheckMac command sequence is running.
led_display_number(0xFF);
// Generate Wakeup pulse. All SHA204 devices that share SDA will wake up.
log_sha204_title("generating 60 us Wakeup low pulse on TWI SDA");
sha204_lib_return = sha204p_wakeup();
if (sha204_lib_return != SHA204_SUCCESS) {
// todo Indicate Wakeup failure.
continue;
}
// Exercise all four devices.
twi_address_client = sha204_i2c_address(i2c_address_index % 4);
i2c_address_index++;
twi_address_host = sha204_i2c_address(i2c_address_index % 4);
i2c_address_index++;
// ---------------------------------------------------------------------------------
// Now let's send a Mac to one SHA204, and verify the generated Mac with a second
// SHA204 serving as a host device. In this example, we are not using the Nonce
// command but the least secure and simplest mode.
// Let host generate a random number to use as Mac challenge. An unlocked SHA204
// will always generate "FFFF0000FFFF0000...".
struct sha204_random_parameters random;
random.mode = 0;
random.tx_buffer = tx_buffer_command;
random.rx_buffer = rx_buffer;
sha204p_set_device_id(twi_address_host);
log_sha204_title("sending Random command to host");
sha204_lib_return = sha204m_random(&random);
log_sha204(random.tx_buffer[SHA204_COUNT_IDX], random.tx_buffer, false);
if (sha204_lib_return != SHA204_SUCCESS) {
sha204_sleep_all();
continue;
}
log_sha204(random.rx_buffer[SHA204_COUNT_IDX], random.rx_buffer, true);
// Save challenge for subsequent CheckMac command.
memcpy(challenge, &random.rx_buffer[SHA204_BUFFER_POS_DATA], sizeof(challenge));
// Send Mac command to client.
struct sha204_mac_parameters mac;
mac.mode = 0;
mac.key_id = 0;
mac.challenge = challenge;
mac.tx_buffer = tx_buffer_command;
mac.rx_buffer = rx_buffer;
sha204p_set_device_id(twi_address_client);
log_sha204_title("sending Mac command to client");
sha204_lib_return = sha204m_mac(&mac);
log_sha204(mac.tx_buffer[SHA204_COUNT_IDX], mac.tx_buffer, false);
if (sha204_lib_return != SHA204_SUCCESS) {
sha204_sleep_all();
continue;
}
log_sha204(mac.rx_buffer[SHA204_COUNT_IDX], mac.rx_buffer, true);
// Save first four bytes of Mac command for subsequent CheckMac command.
memset(other_data, 0, CHECKMAC_OTHER_DATA_SIZE);
memcpy(other_data, &tx_buffer_command[SHA204_OPCODE_IDX], CHECKMAC_CLIENT_COMMAND_SIZE);
// Send CheckMac command to host.
struct sha204_check_mac_parameters check_mac;
check_mac.mode = 0;
check_mac.key_id = 0;
check_mac.client_challenge = challenge;
check_mac.client_response = &rx_buffer[SHA204_BUFFER_POS_DATA];
check_mac.other_data = other_data;
check_mac.tx_buffer = tx_buffer_command;
check_mac.rx_buffer = rx_buffer;
sha204p_set_device_id(twi_address_host);
log_sha204_title("sending CheckMac command to host");
sha204_lib_return = sha204m_check_mac(&check_mac);
log_sha204(check_mac.tx_buffer[SHA204_COUNT_IDX], check_mac.tx_buffer, false);
if (sha204_lib_return != SHA204_SUCCESS) {
sha204_sleep_all();
continue;
}
log_sha204(check_mac.rx_buffer[SHA204_COUNT_IDX], check_mac.rx_buffer, true);
log_sha204_title("sending a Sleep command to all devices");
sha204_sleep_all();
// Display response status byte.
sha204_lib_return = check_mac.rx_buffer[SHA204_BUFFER_POS_STATUS];
}
return sha204_lib_return;
}
//Initialize LCD display
void init_disp (void)
{
static const gpio_map_t DIP204_SPI_GPIO_MAP =
{
{DIP204_SPI_SCK_PIN, DIP204_SPI_SCK_FUNCTION }, // SPI Clock.
{DIP204_SPI_MISO_PIN, DIP204_SPI_MISO_FUNCTION}, // MISO.
{DIP204_SPI_MOSI_PIN, DIP204_SPI_MOSI_FUNCTION}, // MOSI.
{DIP204_SPI_NPCS_PIN, DIP204_SPI_NPCS_FUNCTION} // Chip Select NPCS.
};
// add the spi options driver structure for the LCD DIP204
spi_options_t spiOptions =
{
.reg = DIP204_SPI_NPCS,
.baudrate = 1000000,
.bits = 8,
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 1,
.spi_mode = 0,
.modfdis = 1
};
// Assign I/Os to SPI
gpio_enable_module(DIP204_SPI_GPIO_MAP,
sizeof(DIP204_SPI_GPIO_MAP) / sizeof(DIP204_SPI_GPIO_MAP[0]));
// Initialize as master
spi_initMaster(DIP204_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay
spi_selectionMode(DIP204_SPI, 0, 0, 0);
// Enable SPI
spi_enable(DIP204_SPI);
// setup chip registers
spi_setupChipReg(DIP204_SPI, &spiOptions, FOSC0);
// initialize LCD
dip204_init(backlight_IO, true);
dip204_hide_cursor();
}
int main (void)
{
// Switch the CPU main clock to oscillator 0
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
board_init();
init_disp();
U32 x = 12345678;
U32 y = 87654321;
U64 z =0;
F32 a = 1234.5678;
F32 b = 8765.4321;
F32 c = 0;
U32 calc_time_z = 0;
U32 calc_time_c = 0;
U32 cnt_1 = 0;
U32 cnt_2 = 0;
U32 cnt_3 = 0;
U32 cnt_res_z = 0;
U32 cnt_res_c = 0;
char cycl_str_z[9];
char cycl_str_c[9];
char result[19];
char cycl_c[9];
char cycl_z[9];
//Calculation:
//Cycle count 1
cnt_1 = Get_sys_count();
//Calculation part 1:
z = x*y;
//Cycle count 2
cnt_2 = Get_sys_count();
//Calculation part 2:
c = a*b;
//Cycle count 3
cnt_3 = Get_sys_count();
//Cycle count result
cnt_res_z = cnt_2 - cnt_1 ;
cnt_res_c = cnt_3 - cnt_2 ;
//Use cycle count result to find calculation time
calc_time_c = (cnt_res_c * 1000000 + FOSC0 - 1) / FOSC0;
calc_time_z = (cnt_res_z * 1000000 + FOSC0 - 1) / FOSC0;
//Compose strings for display output
sprintf(result, "%f", c);
sprintf(cycl_str_z, "%lu", calc_time_z);
sprintf(cycl_str_c, "%lu", calc_time_c);
sprintf(cycl_c, "%lu", cnt_res_c);
sprintf(cycl_z, "%lu", cnt_res_z);
//Display calculation time, cycles and multiplication result on monitor
dip204_clear_display();
dip204_set_cursor_position(1,1);
dip204_write_string("x*y=z");
dip204_set_cursor_position(1,2);
dip204_write_string("Time:");
dip204_set_cursor_position(7,2);
dip204_write_string(cycl_str_z);
dip204_set_cursor_position(1,3);
dip204_write_string("Cycles:");
dip204_set_cursor_position(9,3);
dip204_write_string(cycl_z);
dip204_set_cursor_position(11,1);
dip204_write_string("a*b=c");
dip204_set_cursor_position(11,2);
dip204_write_string("Time:");
dip204_set_cursor_position(17,2);
dip204_write_string(cycl_str_c);
dip204_set_cursor_position(11,3);
dip204_write_string("Cycles:");
dip204_set_cursor_position(19,3);
dip204_write_string(cycl_c);
while (1)
{
}
}
/**
\brief The program starts executing here.
*/
int mote_main(void) {
uint8_t i;
// clear local variables
memset(&app_vars,0,sizeof(app_vars_t));
// initialize board
board_init();
// add callback functions radio
radio_setOverflowCb(cb_radioTimerOverflows);
radio_setCompareCb(cb_radioTimerCompare);
radio_setStartFrameCb(cb_startFrame);
radio_setEndFrameCb(cb_endFrame);
// prepare packet
app_vars.packet_len = sizeof(app_vars.packet);
for (i=0;i<app_vars.packet_len;i++) {
app_vars.packet[i] = ID;
}
// start bsp timer
bsp_timer_set_callback(cb_timer);
bsp_timer_scheduleIn(TIMER_PERIOD);
// prepare radio
radio_rfOn();
radio_setFrequency(CHANNEL);
// switch in RX by default
radio_rxEnable();
app_vars.state = APP_STATE_RX;
// start by a transmit
app_vars.flags |= APP_FLAG_TIMER;
while (1) {
// sleep while waiting for at least one of the flags to be set
while (app_vars.flags==0x00) {
board_sleep();
}
// handle and clear every flag
while (app_vars.flags) {
//==== APP_FLAG_START_FRAME (TX or RX)
if (app_vars.flags & APP_FLAG_START_FRAME) {
// start of frame
switch (app_vars.state) {
case APP_STATE_RX:
// started receiving a packet
// led
leds_error_on();
break;
case APP_STATE_TX:
// started sending a packet
// led
leds_sync_on();
break;
}
// clear flag
app_vars.flags &= ~APP_FLAG_START_FRAME;
}
//==== APP_FLAG_END_FRAME (TX or RX)
if (app_vars.flags & APP_FLAG_END_FRAME) {
// end of frame
switch (app_vars.state) {
case APP_STATE_RX:
// done receiving a packet
app_vars.packet_len = sizeof(app_vars.packet);
// get packet from radio
radio_getReceivedFrame(
app_vars.packet,
&app_vars.packet_len,
sizeof(app_vars.packet),
&app_vars.rxpk_rssi,
&app_vars.rxpk_lqi,
&app_vars.rxpk_crc
);
// led
leds_error_off();
break;
case APP_STATE_TX:
// done sending a packet
// switch to RX mode
radio_rxEnable();
app_vars.state = APP_STATE_RX;
// led
leds_sync_off();
break;
}
// clear flag
app_vars.flags &= ~APP_FLAG_END_FRAME;
}
//==== APP_FLAG_TIMER
if (app_vars.flags & APP_FLAG_TIMER) {
// timer fired
if (app_vars.state==APP_STATE_RX) {
// stop listening
radio_rfOff();
// prepare packet
app_vars.packet_len = sizeof(app_vars.packet);
for (i=0;i<app_vars.packet_len;i++) {
app_vars.packet[i] = ID;
}
// start transmitting packet
radio_loadPacket(app_vars.packet,app_vars.packet_len);
radio_txEnable();
radio_txNow();
app_vars.state = APP_STATE_TX;
}
// clear flag
app_vars.flags &= ~APP_FLAG_TIMER;
}
}
}
}