void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mdio_pin_mux); if (board_is_evm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #endif } else if (board_is_sk() || board_is_idk()) { configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) printf("Error: NAND flash not present on this board\n"); #endif configure_module_pin_mux(qspi_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #else configure_module_pin_mux(qspi_pin_mux); #endif } }
void sdram_init(void) { /* * EPOS EVM has 1GB LPDDR2 connected to EMIF. * GP EMV has 1GB DDR3 connected to EMIF * along with VTT regulator. */ if (board_is_eposevm()) { config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); } else if (board_is_evm_14_or_later()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_production, 0); } else if (board_is_evm_12_or_later()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz_beta, 0); } else if (board_is_evm()) { enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs_400Mhz, 0); } else if (board_is_sk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_sk_emif_regs_400Mhz, 0); } else if (board_is_idk()) { config_ddr(400, &ioregs_ddr3, NULL, NULL, &ddr3_idk_emif_regs_400Mhz, 0); } }
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); } return; }
void scale_vcores_generic(u32 m) { int mpu_vdd, ddr_volt; #ifndef CONFIG_DM_I2C if (i2c_probe(TPS65218_CHIP_PM)) return; #else if (power_tps65218_init(0)) return; #endif switch (m) { case 1000: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; break; case 800: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; break; case 720: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; break; case 600: mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; break; case 300: mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; break; default: puts("Unknown MPU clock, not scaling\n"); return; } /* Set DCDC1 (CORE) voltage to 1.1V */ if (tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV)) { printf("%s failure\n", __func__); return; } /* Set DCDC2 (MPU) voltage */ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { printf("%s failure\n", __func__); return; } if (board_is_eposevm()) ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV; else ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV; /* Set DCDC3 (DDR) voltage */ if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) { printf("%s failure\n", __func__); return; } }
const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) return &epos_evm_dpll_ddr; else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; printf(" Board '%s' not supported\n", am43xx_board_name); return NULL; }
int board_fit_config_name_match(const char *name) { if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) return 0; else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) return 0; else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) return 0; else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) return 0; else return -1; }
const struct dpll_params *get_dpll_ddr_params(void) { int ind = get_sys_clk_index(); if (board_is_eposevm()) return &epos_evm_dpll_ddr[ind]; else if (board_is_evm() || board_is_sk()) return &gp_evm_dpll_ddr; else if (board_is_idk()) return &idk_dpll_ddr; printf(" Board '%s' not supported\n", board_ti_get_name()); return NULL; }
void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mdio_pin_mux); if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(qspi_pin_mux); } }
u32 rtc_only_get_board_type(void) { if (board_is_eposevm()) return RTC_BOARD_EPOS; else if (board_is_evm_14_or_later()) return RTC_BOARD_EVM14; else if (board_is_evm_12_or_later()) return RTC_BOARD_EVM12; else if (board_is_gpevm()) return RTC_BOARD_GPEVM; else if (board_is_sk()) return RTC_BOARD_SK; return 0; }
const struct dpll_params *get_dpll_ddr_params(void) { struct am43xx_board_id header; enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_eposevm()) return &epos_evm_dpll_ddr; else if (board_is_gpevm()) return &gp_evm_dpll_ddr; puts(" Board not supported\n"); return NULL; }
int board_fit_config_name_match(const char *name) { bool eeprom_read = board_ti_was_eeprom_read(); if (!strcmp(name, "am4372-generic") && !eeprom_read) return 0; else if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) return 0; else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) return 0; else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) return 0; else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) return 0; else return -1; }
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); } else if (board_is_evm_14_or_later()) { *regs = ext_phy_ctrl_const_base_ddr3_production; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); } else if (board_is_evm_12_or_later()) { *regs = ext_phy_ctrl_const_base_ddr3_beta; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); } else if (board_is_sk()) { *regs = ext_phy_ctrl_const_base_ddr3_sk; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); } return; }
int board_eth_init(bd_t *bis) { int rv; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!env_get("ethaddr")) { puts("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); } mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!env_get("eth1addr")) { if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("eth1addr", mac_addr); } if (board_is_eposevm()) { writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; } else if (board_is_sk()) { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 4; cpsw_slaves[1].phy_addr = 5; } else if (board_is_idk()) { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 0; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 0; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); return rv; }