/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
void c_entry(void)
{
UNS_32 idx;
uart_output_init();
/* Force SSP configuration, use GPIO_05 (SSP0_CS) in software
control mode */
GPIO->p2_dir_set = P2_DIR_GPIO(5);
GPIO->p2_mux_clr = P2_GPIO05_SSEL0;
GPIO->p_mux_set = P_SPI1CLK_SCK0 | P_SPI1DATAIN_SSP0_MISO |
P_SPI1DATAIO_SSP0_MOSI;
board_spi_config();
/* Disable write protect */
spi_flash_wp_disable();
/* Fill first locations with 0's */
for (idx = 0; idx < 8; idx++)
{
board_spi_write(0, idx);
}
uart_output((UNS_8 *)"SPI erased\r\n");
/* Loop forever */
while (1);
}
/***********************************************************************
*
* Function: cfg_save
*
* Purpose: Save a S1L configuration to non-volatile memory
*
* Processing:
* See function.
*
* Parameters:
* pCfg : Pointer to config structure to save
*
* Outputs: None
*
* Returns: Always returns TRUE
*
* Notes: None
*
**********************************************************************/
BOOL_32 cfg_save(S1L_CFG_T *pCfg)
{
UNS_32 idx;
UNS_8 *psspcfg = (UNS_8 *) pCfg;
UNS_8 *data = (UNS_8*)&cfg_check_data;
/* Config SSP for correct mode */
board_spi_config();
cfg_check_data = KEYCHECKVAL;
/* Write configuration structure */
for (idx = 0; idx < sizeof(S1L_CFG_T); idx++)
{
board_spi_write(*psspcfg, (cfg_check_offset + idx));
psspcfg++;
}
/* Write board configuration structure */
psspcfg = (UNS_8 *) &s1l_board_cfg;
for (idx = 0; idx < sizeof(S1L_BOARD_CFG_T); idx++)
{
board_spi_write(*psspcfg, (board_cfg_offset + idx));
psspcfg++;
}
/* Write Configuration Verification Tag */
for(idx = 0; idx < 4; idx++)
{
board_spi_write(data[idx], key_offset + idx);
}
return TRUE;
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
void c_entry(void) {
UNS_8 *p8;
INT_32 toread, idx;
PFV execa = (PFV) STAGE1_LOAD_ADDR;
/* Force SSP configuration, use GPIO_05 (SSP0_CS) in software
control mode */
GPIO->p2_dir_set = P2_DIR_GPIO(5);
GPIO->p2_mux_clr = P2_GPIO05_SSEL0;
GPIO->p_mux_set = P_SPI1CLK_SCK0 | P_SPI1DATAIN_SSP0_MISO |
P_SPI1DATAIO_SSP0_MOSI;
board_spi_config();
/* Read data into memory */
toread = STAGE1_LOAD_SIZE;
p8 = (UNS_8 *) STAGE1_LOAD_ADDR;
idx = SPI_S1APP_OFFSET;
while (toread > 0)
{
*p8 = board_spi_read(idx);
p8++;
idx++;
toread--;
}
#ifdef USE_MMU
dcache_flush();
dcache_inval();
icache_inval();
#endif
execa();
}
/***********************************************************************
*
* Function: cfg_load
*
* Purpose: Load an S1L conmfiguariton from non-volatile memory
*
* Processing:
* See function.
*
* Parameters:
* pCfg : Pointer to config structure to populate
*
* Outputs: None
*
* Returns: FALSE if the structure wasn't loaded, otherwise TRUE
*
* Notes: None
*
**********************************************************************/
BOOL_32 cfg_load(S1L_CFG_T *pCfg)
{
UNS_8 *psspcfg = (UNS_8 *) pCfg;
UNS_8 *cfg = (UNS_8*)&cfg_check_data;
UNS_32 idx = 0;
/* Config SSP for correct mode */
board_spi_config();
/* Read Dummy Byte to Clear FIFO */
*cfg = board_spi_read(idx);
/* Read S1L Configuration & Verification Tag */
for (idx = 0; idx < 4; idx++)
{
*cfg = board_spi_read(key_offset + idx);
cfg++;
}
/* Return False if Verification tag doesn't match */
if (cfg_check_data != KEYCHECKVAL)
return FALSE;
/* Read configuration structure */
for (idx = 0; idx < sizeof(S1L_CFG_T); idx++)
{
*psspcfg = board_spi_read(cfg_check_offset + idx);
psspcfg++;
}
/* Read board configuration structure */
psspcfg = (UNS_8 *) &s1l_board_cfg;
for (idx = 0; idx < sizeof(S1L_BOARD_CFG_T); idx++)
{
*psspcfg = board_spi_read(board_cfg_offset + idx);
psspcfg++;
}
clock_adjust();
return TRUE;
}
