void __init setup_arch(char **cmdline_p)
{
/*
* init "current thread structure" pointer
*/
lm32_current_thread = (struct thread_info*)&init_thread_union;
strlcpy(boot_command_line, cmd_line, COMMAND_LINE_SIZE);
*cmdline_p = cmd_line;
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_EARLY_PRINTK
setup_early_printk();
#endif
/*
* Init boot memory
*/
bootmem_init();
device_tree_init();
/*
* Get kmalloc into gear.
*/
paging_init();
}
void __init setup_arch(char **cmdline_p)
{
/*
* init "current thread structure" pointer
*/
lm32_current_thread = (struct thread_info*)&init_thread_union;
/* populate memory_start and memory_end, needed for bootmem_init() */
early_init_devtree(__dtb_start);
/* a cmdline set by the bootloader overrides one defined in the dts */
if (__cmdline && strlen(__cmdline))
strlcpy(cmd_line, __cmdline, COMMAND_LINE_SIZE);
*cmdline_p = cmd_line;
strlcpy(boot_command_line, cmd_line, COMMAND_LINE_SIZE);
/* early commandline needed by memblock */
parse_early_param();
bootmem_init();
device_tree_init();
paging_init();
plat_setup_arch();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
printk("Determined physical RAM map:\n");
print_memory_map();
strlcpy(command_line, arcs_cmdline, sizeof(command_line));
strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
printk("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
#ifdef CONFIG_SPARSEMEM
sparse_memory_present_with_active_regions(MAX_NUMNODES);
#endif
sparse_init();
paging_init();
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
pr_info("Determined physical RAM map:\n");
print_memory_map();
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
device_tree_init();
sparse_init();
plat_swiotlb_setup();
paging_init();
}
void __init setup_arch(char **cmdline_p)
{
#ifdef CONFIG_SGI_IP22
ip22_setup();
#endif
#ifdef CONFIG_SGI_IP27
ip27_setup();
#endif
#ifdef CONFIG_SGI_IP32
ip32_setup();
#endif
#ifdef CONFIG_SIBYTE_SWARM
swarm_setup();
#endif
#ifdef CONFIG_MIPS_MALTA
malta_setup();
#endif
strncpy(command_line, arcs_cmdline, CL_SIZE);
memcpy(saved_command_line, command_line, CL_SIZE);
saved_command_line[CL_SIZE-1] = '\0';
*cmdline_p = command_line;
parse_mem_cmdline();
bootmem_init();
paging_init();
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
pr_info("Determined physical RAM map:\n");
print_memory_map();
strlcpy(command_line, arcs_cmdline, sizeof(command_line));
strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
#ifndef CONFIG_NLM_16G_MEM_SUPPORT
#ifndef CONFIG_NUMA
setup_mapped_kernel_tlbs(FALSE, TRUE);
#endif
#endif
sparse_init();
paging_init();
}
void __init setup_arch(char **cmdline_p)
{
extern int mem_reserve(unsigned long, unsigned long, int);
extern void bootmem_init(void);
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
*cmdline_p = command_line;
/* Reserve some memory regions */
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start < initrd_end) {
initrd_is_mapped = mem_reserve(__pa(initrd_start),
__pa(initrd_end), 0);
initrd_below_start_ok = 1;
} else {
initrd_start = 0;
}
#endif
mem_reserve(__pa(&_stext),__pa(&_end), 1);
mem_reserve(__pa(&_WindowVectors_text_start),
__pa(&_WindowVectors_text_end), 0);
mem_reserve(__pa(&_DebugInterruptVector_literal_start),
__pa(&_DebugInterruptVector_text_end), 0);
mem_reserve(__pa(&_KernelExceptionVector_literal_start),
__pa(&_KernelExceptionVector_text_end), 0);
mem_reserve(__pa(&_UserExceptionVector_literal_start),
__pa(&_UserExceptionVector_text_end), 0);
mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
__pa(&_DoubleExceptionVector_text_end), 0);
bootmem_init();
platform_setup(cmdline_p);
paging_init();
zones_init();
#ifdef CONFIG_VT
# if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
# elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
# endif
#endif
#ifdef CONFIG_PCI
platform_pcibios_init();
#endif
}
void __init setup_arch(char **cmdline_p)
{
struct tag *tags = (struct tag *)&init_tags;
char *from = default_command_line;
setup_processor();
if(machine_arch_type == MACH_TYPE_A5K)
machine_name = "A5000";
else if(machine_arch_type == MACH_TYPE_ARCHIMEDES)
machine_name = "Archimedes";
else
machine_name = "UNKNOWN";
//FIXME - the tag struct is always copied here but this is a block
// of RAM that is accidentally reserved along with video RAM. perhaps
// it would be a good idea to explicitly reserve this?
tags = (struct tag *)0x0207c000;
/*
* If we have the old style parameters, convert them to
* a tag list.
*/
if (tags->hdr.tag != ATAG_CORE)
convert_to_tag_list(tags);
if (tags->hdr.tag != ATAG_CORE)
tags = (struct tag *)&init_tags;
if (tags->hdr.tag == ATAG_CORE) {
if (meminfo.nr_banks != 0)
squash_mem_tags(tags);
parse_tags(tags);
}
init_mm.start_code = (unsigned long) &_text;
#ifndef CONFIG_XIP_KERNEL
init_mm.end_code = (unsigned long) &_etext;
#else
init_mm.end_code = (unsigned long) &_endtext;
init_mm.start_data = (unsigned long) &_sdata;
#endif
init_mm.end_data = (unsigned long) &_edata;
init_mm.brk = (unsigned long) &_end;
memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
parse_cmdline(&meminfo, cmdline_p, from);
bootmem_init(&meminfo);
paging_init(&meminfo);
request_standard_resources(&meminfo);
#ifdef CONFIG_VT
#if defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
}
void __init setup_arch(char **cmdline_p)
{
randomize_va_space = 0;
*cmdline_p = command_line;
cpu_cache_init();
tlb_init();
bootmem_init();
paging_init();
resource_init();
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
phys_t init_mem, init_end, init_size;
/* call board setup routine */
plat_mem_setup();
init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
init_size = init_end - init_mem;
if (init_size) {
/* Make sure it is in the boot_mem_map */
int i, found;
found = 0;
for (i = 0; i < boot_mem_map.nr_map; i++) {
if (init_mem >= boot_mem_map.map[i].addr &&
init_mem < (boot_mem_map.map[i].addr +
boot_mem_map.map[i].size)) {
found = 1;
break;
}
}
if (!found)
add_memory_region(init_mem, init_size,
BOOT_MEM_INIT_RAM);
}
printk("Determined physical RAM map:\n");
print_memory_map();
strlcpy(command_line, arcs_cmdline, sizeof(command_line));
strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
printk("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
sparse_init();
paging_init();
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
pr_info("Determined physical RAM map:\n");
print_memory_map();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
#else
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
#if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_RT2880_DRAM_512M)
reserve_bootmem(0x1C000000, 64*1024*1024, BOOTMEM_DEFAULT);
#endif
device_tree_init();
sparse_init();
plat_swiotlb_setup();
paging_init();
}
void __init setup_arch(char **cmdline_p)
{
/*
* init "current thread structure" pointer
*/
lm32_current_thread = (struct thread_info*)&init_thread_union;
cpu_frequency = (unsigned long)CONFIG_CPU_CLOCK;
sdram_start = (unsigned long)CONFIG_MEMORY_START;
sdram_size = (unsigned long)CONFIG_MEMORY_SIZE;
/* Keep a copy of command line */
*cmdline_p = (char*)_kernel_arg_cmdline;
#if defined(CONFIG_BOOTPARAM)
/* CONFIG_CMDLINE should override all */
strncpy(*cmdline_p, CONFIG_BOOTPARAM_STRING, COMMAND_LINE_SIZE);
#endif
memcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE-1] = 0;
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_EARLY_PRINTK
{
extern void setup_early_printk(void);
setup_early_printk();
}
#endif
/*
* Init boot memory
*/
bootmem_init();
/*
* Get kmalloc into gear.
*/
paging_init();
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
pr_info("Determined physical RAM map:\n");
print_memory_map();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
#else
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
sparse_init();
paging_init();
#ifdef CONFIG_DUMP_PREV_OOPS_MSG
reserve_bootmem(CPHYSADDR(CONFIG_DUMP_PREV_OOPS_MSG_BUF_ADDR), CONFIG_DUMP_PREV_OOPS_MSG_BUF_LEN, BOOTMEM_DEFAULT);
#endif
}
static void __init arch_mem_init(char **cmdline_p)
{
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
pr_info("Determined physical RAM map:\n");
print_memory_map();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
#else
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
device_tree_init();
sparse_init();
paging_init();
}
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
struct lb_header *head;
if (low_table_start || low_table_end) {
printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
low_table_end);
head = lb_table_init(low_table_end);
lb_forward(head, (struct lb_header*)rom_table_end);
low_table_end = (unsigned long) lb_table_fini(head);
printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n",
low_table_end);
low_table_end = ALIGN(low_table_end, 4096);
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end);
}
printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n",
rom_table_end);
head = lb_table_init(rom_table_end);
rom_table_end = (unsigned long)head;
printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
rom_table_end = ALIGN(rom_table_end, (64 * 1024));
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
#if CONFIG_USE_OPTION_TABLE
{
struct cmos_option_table *option_table =
cbfs_boot_map_with_leak("cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT, NULL);
if (option_table) {
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a lb_record... */
memcpy(rec_dest, option_table, option_table->size);
/* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
} else {
printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
}
}
#endif
/* Initialize the memory map at boot time. */
bootmem_init();
if (low_table_start || low_table_end) {
uint64_t size = low_table_end - low_table_start;
/* Record the mptable and the the lb_table.
* (This will be adjusted later) */
bootmem_add_range(low_table_start, size, LB_MEM_TABLE);
}
/* Record the pirq table, acpi tables, and maybe the mptable. However,
* these only need to be added when the rom_table is sitting below
* 1MiB. If it isn't that means high tables are being written.
* The code below handles high tables correctly. */
if (rom_table_end <= (1 << 20)) {
uint64_t size = rom_table_end - rom_table_start;
bootmem_add_range(rom_table_start, size, LB_MEM_TABLE);
}
/* No other memory areas can be added after the memory table has been
* committed as the entries won't show up in the serialize mem table. */
bootmem_write_memory_table(lb_memory(head));
/* Record our motherboard */
lb_mainboard(head);
/* Record the serial ports and consoles */
#if CONFIG_CONSOLE_SERIAL
uart_fill_lb(head);
#endif
#if CONFIG_CONSOLE_USB
lb_add_console(LB_TAG_CONSOLE_EHCI, head);
#endif
/* Record our various random string information */
lb_strings(head);
lb_record_version_timestamp(head);
/* Record our framebuffer */
lb_framebuffer(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
/* pass along the VDAT buffer address */
lb_vdat(head);
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
#endif
/* Add board ID if available */
lb_board_id(head);
/* Add RAM config if available */
lb_ram_code(head);
#if IS_ENABLED(CONFIG_SPI_FLASH)
/* Add SPI flash description if available */
lb_spi_flash(head);
#endif
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */
lb_board(head);
#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
lb_ramoops(head);
#endif
lb_boot_media_params(head);
/* Add all cbmem entries into the coreboot tables. */
cbmem_add_records_to_cbtable(head);
/* Remember where my valid memory ranges are */
return lb_table_fini(head);
}
void __init setup_arch(char **cmdline_p)
{
strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
check_s32c1i();
/* Reserve some memory regions */
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start < initrd_end) {
initrd_is_mapped = mem_reserve(__pa(initrd_start),
__pa(initrd_end), 0);
initrd_below_start_ok = 1;
} else {
initrd_start = 0;
}
#endif
mem_reserve(__pa(&_stext),__pa(&_end), 1);
mem_reserve(__pa(&_WindowVectors_text_start),
__pa(&_WindowVectors_text_end), 0);
mem_reserve(__pa(&_DebugInterruptVector_literal_start),
__pa(&_DebugInterruptVector_text_end), 0);
mem_reserve(__pa(&_KernelExceptionVector_literal_start),
__pa(&_KernelExceptionVector_text_end), 0);
mem_reserve(__pa(&_UserExceptionVector_literal_start),
__pa(&_UserExceptionVector_text_end), 0);
mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
__pa(&_DoubleExceptionVector_text_end), 0);
#if XCHAL_EXCM_LEVEL >= 2
mem_reserve(__pa(&_Level2InterruptVector_text_start),
__pa(&_Level2InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 3
mem_reserve(__pa(&_Level3InterruptVector_text_start),
__pa(&_Level3InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 4
mem_reserve(__pa(&_Level4InterruptVector_text_start),
__pa(&_Level4InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 5
mem_reserve(__pa(&_Level5InterruptVector_text_start),
__pa(&_Level5InterruptVector_text_end), 0);
#endif
#if XCHAL_EXCM_LEVEL >= 6
mem_reserve(__pa(&_Level6InterruptVector_text_start),
__pa(&_Level6InterruptVector_text_end), 0);
#endif
bootmem_init();
#ifdef CONFIG_OF
copy_devtree();
unflatten_device_tree();
#endif
platform_setup(cmdline_p);
paging_init();
zones_init();
#ifdef CONFIG_VT
# if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
# elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
# endif
#endif
#ifdef CONFIG_PCI
platform_pcibios_init();
#endif
}
void __init setup_arch(char **cmdline_p)
{
extern void atlas_setup(void);
extern void decstation_setup(void);
extern void ip22_setup(void);
extern void ip27_setup(void);
extern void malta_setup(void);
extern void momenco_ocelot_setup(void);
extern void momenco_ocelot_g_setup(void);
extern void momenco_ocelot_c_setup(void);
extern void momenco_jaguar_atx_setup(void);
extern void sead_setup(void);
extern void swarm_setup(void);
extern void frame_info_init(void);
frame_info_init();
#ifdef CONFIG_MIPS_ATLAS
atlas_setup();
#endif
#ifdef CONFIG_DECSTATION
decstation_setup();
#endif
#ifdef CONFIG_PMC_YOSEMITE
pmc_yosemite_setup();
#endif
#ifdef CONFIG_SGI_IP22
ip22_setup();
#endif
#ifdef CONFIG_SGI_IP27
ip27_setup();
#endif
#ifdef CONFIG_SIBYTE_BOARD
swarm_setup();
#endif
#ifdef CONFIG_MIPS_MALTA
malta_setup();
#endif
#ifdef CONFIG_MIPS_SEAD
sead_setup();
#endif
#ifdef CONFIG_MOMENCO_OCELOT
momenco_ocelot_setup();
#endif
#ifdef CONFIG_MOMENCO_OCELOT_G
momenco_ocelot_g_setup();
#endif
#ifdef CONFIG_MOMENCO_OCELOT_C
momenco_ocelot_c_setup();
#endif
#ifdef CONFIG_MOMENCO_JAGUAR_ATX
momenco_jaguar_atx_setup();
#endif
strncpy(command_line, arcs_cmdline, CL_SIZE);
memcpy(saved_command_line, command_line, CL_SIZE);
saved_command_line[CL_SIZE-1] = '\0';
*cmdline_p = command_line;
parse_mem_cmdline();
bootmem_init();
paging_init();
resource_init();
}
void __init setup_arch(char **cmdline_p)
{
struct tag *tags = (struct tag *)&init_tags;
struct machine_desc *mdesc;
char *from = default_command_line;
ROOT_DEV = MKDEV(0, 255);
setup_processor();
mdesc = setup_machine(machine_arch_type);
machine_name = mdesc->name;
if (mdesc->soft_reboot)
reboot_setup("s");
if (mdesc->param_offset)
tags = phys_to_virt(mdesc->param_offset);
/*
* Do the machine-specific fixups before we parse the
* parameters or tags.
*/
if (mdesc->fixup)
mdesc->fixup(mdesc, (struct param_struct *)tags,
&from, &meminfo);
/*
* If we have the old style parameters, convert them to
* a tag list.
*/
if (tags->hdr.tag != ATAG_CORE)
convert_to_tag_list(tags);
if (tags->hdr.tag == ATAG_CORE) {
if (meminfo.nr_banks != 0)
squash_mem_tags(tags);
parse_tags(tags);
}
if (meminfo.nr_banks == 0) {
meminfo.nr_banks = 1;
meminfo.bank[0].start = PHYS_OFFSET;
meminfo.bank[0].size = MEM_SIZE;
}
init_mm.start_code = (unsigned long) &_text;
init_mm.end_code = (unsigned long) &_etext;
init_mm.end_data = (unsigned long) &_edata;
init_mm.brk = (unsigned long) &_end;
memcpy(saved_command_line, from, COMMAND_LINE_SIZE);
saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
parse_cmdline(&meminfo, cmdline_p, from);
bootmem_init(&meminfo);
paging_init(&meminfo, mdesc);
request_standard_resources(&meminfo, mdesc);
/*
* Set up various architecture-specific pointers
*/
init_arch_irq = mdesc->init_irq;
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
}
static void __init arch_mem_init(char **cmdline_p)
{
phys_t init_mem, init_end, init_size;
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
init_size = init_end - init_mem;
if (init_size) {
/* Make sure it is in the boot_mem_map */
int i, found;
found = 0;
for (i = 0; i < boot_mem_map.nr_map; i++) {
if (init_mem >= boot_mem_map.map[i].addr &&
init_mem < (boot_mem_map.map[i].addr +
boot_mem_map.map[i].size)) {
found = 1;
break;
}
}
if (!found)
add_memory_region(init_mem, init_size,
BOOT_MEM_INIT_RAM);
}
pr_info("Determined physical RAM map:\n");
print_memory_map();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
#else
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
device_tree_init();
sparse_init();
plat_swiotlb_setup();
paging_init();
}
