/*
* Broadcom specific IRQ setup
*/
void __init arch_init_irq(void)
{
int irq;
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = ~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK);
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type;
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type;
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_PERFCOUNT_IRQ].chip = &brcm_mips_performance_type;
brcm_mips_performance_enable(0);
#endif
brcm_mips_int2_enable(0);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1, shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = CPUINT1C->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus);
//if (pendingIrqs == HYDRA_UART0_INTR_MASK)
// do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
//else
// printk("unsolicited interrupt!!!\n");
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT)
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
#ifdef CONFIG_KGDB
else if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ub_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_MASK) )
{
//printk("@@@@@@@UARTB IRQ %d\n", irq);
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
#endif
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++)
{
shift = irq - 32 -1;
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
brcm_mips_int2_enable(0);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = INTC->IrqStatus & INTC->IrqMask;
/* IRQs from 1 to 32 - 0 reserved for main IRQ and 60 for timer */
for (irq = 1; irq <= 32; ++irq)
{
shift = irq -1;
if ((0x1 << shift) & pendingIrqs)
{
if (irq == BCM_LINUX_UPG_IRQ) {
if (UPG_INTC->irqstat_l & UPG_INTC->irqen_l & UPG_UA_IRQ) {
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (UPG_INTC->irqstat_l & UPG_INTC->irqen_l & UPG_SCA_IRQ) {
//printk("Calling do_IRQ for SCA, INTC.stats=%08x, INTC.mask=%08x @%08x, called=%x\n",
// INTC->IrqStatus, INTC->IrqMask, &INTC->IrqStatus, doIrqCalled);
//doIrqCalled |=2;
do_IRQ(BCM_LINUX_SCA_IRQ, regs);
}
else if (UPG_INTC->irqstat_l & UPG_INTC->irqen_l & UPG_SCB_IRQ) {
//printk("Calling do_IRQ for SCB, INTC.stats=%08x, INTC.mask=%08x @%08x, called=%x\n",
// INTC->IrqStatus, INTC->IrqMask, &INTC->IrqStatus, doIrqCalled);
//doIrqCalled |= 4;
do_IRQ(BCM_LINUX_SCB_IRQ, regs);
}
else {
do_IRQ(BCM_LINUX_UPG_IRQ, regs);
}
}
else if (irq == BCM_LINUX_DMA_IRQ || irq == BCM_LINUX_MODEM_IRQ)
brcm_dma_dispatch(irq,regs);
else
do_IRQ(irq, regs);
++g_brcm_intc_cnt[shift];
}
}
brcm_mips_int2_enable(0);
}
static void brcm_mips_int2_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
brcm_mips_int2_enable(irq);
}
static unsigned int brcm_mips_int2_startup(unsigned int irq)
{
brcm_mips_int2_enable(irq);
return 0; /* never anything pending */
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern int noirqdebug;
printk("timer irq %d\n", BCM_LINUX_SYSTIMER_IRQ);
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff;
CPUINT1C->IntrW2MaskSet = 0xffffffff;
change_c0_status(ST0_IE, 0);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type;
DECLARE_SMTC_IRQ(BCM_LINUX_SYSTIMER_IRQ, 7);
PRINTK("setup timer int\n");
#if defined(CONFIG_SMP) && ! defined(CONFIG_MIPS_MT)
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].chip = &brcm_mips_int7_type;
/* S/W IPC interrupt */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].chip = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].chip = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 96; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
DECLARE_SMTC_IRQ(irq, 2);
g_brcm_intc_cnt[irq -1] = 0;
}
PRINTK("setup int 1 to 96\n");
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTA_IRQ, 2);
PRINTK("setup UARTA int\n");
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTB_IRQ, 2);
PRINTK("setup UARTB int\n");
noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also).
brcm_mips_int2_enable(0);
//enable the UPG level UARTA int.
*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) |= BCHP_IRQ0_IRQEN_uarta_irqen_MASK;
#ifdef CONFIG_MIPS_MT_SMTC
local_irq_disable(); /* set IXMT for this TC */
change_c0_status(ST0_IE, 1); /* global IE = 1 */
PRINTK("disable irq\n");
#endif
#ifdef CONFIG_MIPS_MT
/* NOTE: vectored interrupts are not properly supported yet */
set_vi_handler(2, plat_irq_dispatch);
set_vi_handler(7, plat_irq_dispatch);
PRINTK("set vi handler for int2 and 7\n");
#endif
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1,pendingIrqs2, shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = CPUINT1C->IntrW0Status;
pendingIrqs1 = CPUINT1C->IntrW1Status;
pendingIrqs2 = CPUINT1C->IntrW2Status;
#ifdef DEBUG_UARTA_INTR
#ifdef DEBUG_UARTA_INTR_FROM_INT2IRQ
dump_INTC_regs();
#endif
gDebugPendingIrq0 = pendingIrqs &= ~(gDebugMaskW0 = CPUINT1C->IntrW0MaskStatus);
gDebugPendingIrq1 = pendingIrqs1 &= ~(gDebugMaskW1 = CPUINT1C->IntrW1MaskStatus);
gDebugPendingIrq2 = pendingIrqs2 &= ~(gDebugMaskW2 = CPUINT1C->IntrW2MaskStatus);
#endif // DEBUG_UARTA_INTR
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT) {
PRINTK("UART A\n");
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) )
{
PRINTK("UART B\n");
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) )
{
PRINTK("UART C\n");
do_IRQ(BCM_LINUX_UARTC_IRQ, regs);
}
else if (irq == BCM_LINUX_CPU_ENET_IRQ)
{
#ifndef CONFIG_MIPS_BRCM_IKOS
if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 )
do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs);
else
#endif
printk("unsolicited ENET interrupt!!!\n");
}
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 -1;
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
for (irq = 64+1; irq <= 64+32; irq++)
{
shift = irq - 64 -1;
if ((0x1 << shift) & pendingIrqs2)
do_IRQ(irq, regs);
}
brcm_mips_int2_enable(0);
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern asmlinkage void brcmIRQ(void);
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = ~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK);
set_except_vector(0, brcmIRQ);
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].handler = &brcm_mips_int7_type;
/* Install all the 7xxx IRQs */
#if 1
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
#endif
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].handler = &brcm_uart_type;
#ifdef CONFIG_KGDB
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].handler = &brcm_uart_type;
#endif
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_PERFCOUNT_IRQ].handler = &brcm_mips_performance_type;
brcm_mips_performance_enable(0);
#endif
brcm_mips_int2_enable(0);
//enable the UPG level UARTA int.
//*((volatile unsigned long*)BCHP_IRQ0_UARTA_IRQEN) |= BCHP_IRQ0_UARTA_IRQEN_uarta_MASK;
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern int noirqdebug;
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff;
//CPUINT1C->IntrW2MaskSet = 0xffffffff;
change_c0_status(ST0_IE, 0);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int6_type;
#ifdef CONFIG_SMP
/* Setup 2nd timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].chip = &brcm_mips_int6_type;
/* S/W IPC interrupt */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].chip = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].chip = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
DECLARE_SMTC_IRQ(irq, 2);
g_brcm_intc_cnt[irq -1] = 0;
}
PRINTK("setup int 1 to 96\n");
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTA_IRQ, 2);
PRINTK("setup UARTA int\n");
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTB_IRQ, 2);
PRINTK("setup UARTB int\n");
irq_desc[BCM_LINUX_UARTC_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTC_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTC_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTC_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTC_IRQ, 2);
PRINTK("setup UARTB int\n");
irq_desc[BCM_LINUX_UARTD_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTD_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTD_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTD_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTD_IRQ, 2);
PRINTK("setup UARTB int\n");
#if 0
/* Set up smartcard interrupts. */
irq_desc[BCM_LINUX_SCA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCA_IRQ].action = 0;
irq_desc[BCM_LINUX_SCA_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCA_IRQ].chip = &brcm_intc_type;
irq_desc[BCM_LINUX_SCB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCB_IRQ].action = 0;
irq_desc[BCM_LINUX_SCB_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCB_IRQ].chip = &brcm_intc_type;
#endif
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].chip = &brcm_mips_int7_type;
//brcm_mips_performance_enable(0);
#endif
#if 0
/* Not on 7443 */
irq_desc[BCM_LINUX_PATA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PATA_IRQ].action = 0;
irq_desc[BCM_LINUX_PATA_IRQ].depth = 1;
irq_desc[BCM_LINUX_PATA_IRQ].chip = &brcm_pata_type;
#endif
noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also).
brcm_mips_int2_enable(0);
//enable the UPG level UARTA int.
*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) |= BCHP_IRQ0_IRQEN_uarta_irqen_MASK;
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1, shift,irq;
brcm_mips_int2_disable(0);
#ifdef CONFIG_MIPS_BCM7601B_SECOND_CPU
pendingIrqs = CPUINT1C_TP1->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C_TP1->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C_TP1->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C_TP1->IntrW1MaskStatus);
#else
pendingIrqs = CPUINT1C->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus);
#endif
//printk("pending irqs=%x\n",pendingIrqs);
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT) {
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT) {
if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTC_IRQ, regs);
}
if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_udirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ud_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTD_IRQ, regs);
}
do_IRQ(irq, regs);
}
else if (irq == BCM_LINUX_CPU_ENET_IRQ)
{
#ifndef CONFIG_MIPS_BRCM_SIM
if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 )
do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs);
else
printk("unsolicited ENET interrupt!!!\n");
#endif
}
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 -1;
#if 0 //vincent
//#ifndef CONFIG_MIPS_BRCM_SIM
if (shift == BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IDE_CPU_INTR_SHIFT)
{
unsigned long l2status = *((volatile unsigned long*)BCM_PATA_IRQ_CPU_STATUS);
if (l2status & BCHP_IDE_L2_CPU_STATUS_IDE_PRI_INT_MASK)
{
do_IRQ(BCM_LINUX_PATA_IRQ, regs);
}
}
else
#endif
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
brcm_mips_int2_enable(0);
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern asmlinkage void brcmIRQ(void);
extern int noirqdebug;
//printk("timer irq %d end %d\n",BCM_LINUX_SYSTIMER_IRQ, BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_reserved0_SHIFT+32);
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff; //~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK);
set_except_vector(0, brcmIRQ);
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].handler = &brcm_mips_int7_type;
#ifdef CONFIG_SMP
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].handler = &brcm_mips_int7_type;
/* S/W IPC interrupt */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].handler = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].handler = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].handler = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].handler = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTC_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTC_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTC_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTC_IRQ].handler = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTD_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTD_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTD_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTD_IRQ].handler = &brcm_uart_type;
#if 0
/* Set up smartcard interrupts. */
irq_desc[BCM_LINUX_SCA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCA_IRQ].action = 0;
irq_desc[BCM_LINUX_SCA_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCA_IRQ].handler = &brcm_intc_type;
irq_desc[BCM_LINUX_SCB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCB_IRQ].action = 0;
irq_desc[BCM_LINUX_SCB_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCB_IRQ].handler = &brcm_intc_type;
#endif
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].handler = &brcm_mips_performance_type;
//brcm_mips_performance_enable(0);
#endif
irq_desc[BCM_LINUX_PATA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PATA_IRQ].action = 0;
irq_desc[BCM_LINUX_PATA_IRQ].depth = 1;
irq_desc[BCM_LINUX_PATA_IRQ].handler = &brcm_pata_type;
noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also).
brcm_mips_int2_enable(0);
#if 1 //#ifdef CONFIG_MIPS_BRCM_IKOS
//enable the UPG level UARTA int.
*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) |= BCHP_IRQ0_IRQEN_uarta_irqen_MASK;
//INTC->IrqMask |= 0x1UL << (BCM_LINUX_UPG_IRQ -1);
#endif
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern asmlinkage void brcmIRQ(void);
INTC->IrqMask = 0UL;
INTC->IrqStatus = 0UL;
set_except_vector(0, brcmIRQ);
/* IMHO we do not need to do the following here, the request IRQ would take care of it. */
//change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); // right now we only care about IRQ0 and 5.
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].handler = &brcm_mips_int7_type;
/* Install all the 7xxx IRQs */
/* IRQs from 1 to 32 - 0 reserved for main IRQ and 60 for timer */
for (irq = 1; irq <= 32; ++irq)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].handler = &brcm_uart_type;
/* Set up soft modem interrupts. */
irq_desc[BCM_LINUX_SOFT_MODEM_DMA_IRQS].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SOFT_MODEM_DMA_IRQS].action = 0;
irq_desc[BCM_LINUX_SOFT_MODEM_DMA_IRQS].depth = 1;
irq_desc[BCM_LINUX_SOFT_MODEM_DMA_IRQS].handler = &brcm_intc_type;
/* Set up smartcard interrupts. */
irq_desc[BCM_LINUX_SCA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCA_IRQ].action = 0;
irq_desc[BCM_LINUX_SCA_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCA_IRQ].handler = &brcm_intc_type;
irq_desc[BCM_LINUX_SCB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCB_IRQ].action = 0;
irq_desc[BCM_LINUX_SCB_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCB_IRQ].handler = &brcm_intc_type;
/* Setup external 4413 interrupts */
irq_desc[BCM_LINUX_4413ENET_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_4413ENET_IRQ].action = 0;
irq_desc[BCM_LINUX_4413ENET_IRQ].depth = 1;
irq_desc[BCM_LINUX_4413ENET_IRQ].handler = &brcm_mips_int6_type;
brcm_mips_int2_enable(0);
INTC->IrqMask |= 0x1UL << (BCM_LINUX_UPG_IRQ -1);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1, shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = CPUINT1C->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus);
//if (pendingIrqs == HYDRA_UART0_INTR_MASK)
// do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
//else
// printk("unsolicited interrupt!!!\n");
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (irq == BCM_LINUX_CPU_ENET_IRQ)
{
//if (*((volatile unsigned long *)0xb0082418) & 0x2 )
if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 )
do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs);
else
printk("unsolicited ENET interrupt!!!\n");
}
else if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTC_IRQ, regs);
}
else if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_uairq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ua_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 -1;
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
#if 0
if (g_intcnt++ >= 0xFFFF)
{
g_intcnt = 0;
for (irq = 1; irq <= 32; ++irq)
{
if (m_intc_cnt[irq - 1] != 0)
printk("IRQ[%d] count = %d\n",irq,g_brcm_intc_cnt[irq - 1]);
}
}
#endif
brcm_mips_int2_enable(0);
}
