END_TEST
/**
* Make sure things are sometimes accepted and sometimes not.
*
* Note this test assumes (incorrectly, but practically) that the probability of
* all zeros or all ones is 0.0. If the test fails, double check that the random
* numbers generated aren't the cause.
*/
START_TEST (test_50_50)
{
INIT_CON(); SET_CON_BERNOULLI(0.5);
// Fill the buffer with packets, some of which will be accepted
for (int i = 0; i < BUFFER_SIZE; i++)
buffer_push(&b, spinn_packet_pool_palloc(&pool));
for (int i = 0; i < PERIOD * BUFFER_SIZE; i++)
scheduler_tick_tock(&s);
// Make sure some packets got accepted and others didn't
ck_assert(!buffer_is_empty(&b));
ck_assert(!buffer_is_full(&b));
ck_assert(packets_received > 0);
ck_assert(packets_received < BUFFER_SIZE);
}
void buffer_add(bufferADT buffer, char c) {
if(buffer_is_full(buffer)) {
buffer_consume(buffer);
}
buffer->mem_start[buffer->head] = c;
buffer->head = buffer_next_index(buffer, buffer->head);
}
void uart1_write(uint8_t byte)
{
if ((UCSR1A & (1 << UDRE1)) && buffer_count(&buffer_tx1) == 0)
{
UDR1 = byte; // write buffer empty and no uart write in progress -> write out directly
return;
}
while (buffer_is_full(&buffer_tx1)); // write buffer full - wait!
uart1_int_disable();
buffer_write(&buffer_tx1, byte);
uart1_int_enable();
}
void uart0_write(uint8_t byte)
{
if (buffer_count(&buffer_tx0) == 0 && (UCSR0A & (1 << UDRE0)))
{
UDR0 = byte; // write buffer empty and no uart write in progress -> write out directly
return;
}
while (buffer_is_full(&buffer_tx0)); // write buffer full - wait!
uart0_int_disable();
buffer_write(&buffer_tx0, byte);
uart0_int_enable();
}
void produce()
{
int i;
int item;
for (i = 0; i < ITEM_COUNT; i++) {
pthread_mutex_lock(&mutex);
while (buffer_is_full())
pthread_cond_wait(&wait_empty_buffer, &mutex);
item = i + 'a';
printf("produce item: %c\n", item);
put_item(item);
sleep(1);
pthread_cond_signal(&wait_full_buffer);
pthread_mutex_unlock(&mutex);
}
}
/* producer thread */
void *producer(void *arg)
{
long int i;
long int loops = (long int)arg;
for (i=0; i<loops; i++) {
pthread_mutex_lock(&mutex);
if (buffer_is_full())
pthread_cond_wait(&cond, &mutex);
buffer_put(i);
pthread_cond_signal(&cond);
pthread_mutex_unlock(&mutex);
}
return NULL;
}
void uart0_write_buffer(const uint8_t *data, uint8_t size)
{
uint8_t i = 0;
if (buffer_count(&buffer_tx0) == 0 && (UCSR0A & (1 << UDRE0)))
{
if (size > 1)
{
UCSR0B &= (uint8_t)~((1 << TXCIE0)); // disable tx interrupt to have at least 1 byte in tx buffer before interrupt handler is called
}
UDR0 = data[i++]; // write buffer empty and no uart write in progress -> write out first byte directly
}
while (i < size)
{
while (buffer_is_full(&buffer_tx0))
{
UCSR0B |= (1 << TXCIE0); // write buffer full, enable tx irq to send out data and wait...
}
UCSR0B &= (uint8_t)~((1 << TXCIE0)); // disable transmit interrupt to protect tx buffer
buffer_write(&buffer_tx0, data[i]);
++i;
}
UCSR0B |= (1 << TXCIE0); // enable transmit interrupt
}
END_TEST
/**
* Ensure with a periodic interval, packets are consumed at the correct times when
* the input is not blocked.
*/
START_TEST (test_periodic_free)
{
INIT_CON();
SET_CON_PERIODIC(INTERVAL);
// Fill the buffer with packets
for (int i = 0; i < BUFFER_SIZE; i++)
buffer_push(&b, spinn_packet_pool_palloc(&pool));
// Run for long enough that the buffer ends up empty
for (int i = 0; i < BUFFER_SIZE; i++) {
// Run the consumer for a single interval until the end of which no packets
// should be received
for (int j = 0; j < INTERVAL; j++) {
ck_assert_int_eq(packets_received, i);
for (int k = 0; k < PERIOD; k++) {
scheduler_tick_tock(&s);
}
}
// A packet should have been received by now
ck_assert(!buffer_is_full(&b));
ck_assert_int_eq(packets_received, i+1);
}
// The buffer should end up empty
ck_assert(buffer_is_empty(&b));
ck_assert_int_eq(packets_received, BUFFER_SIZE);
}
