void HitachiDSP::enter() {
while(true) {
// exit requested due to savestate
if(scheduler.sync == Scheduler::SynchronizeMode::All) {
scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
}
// if we bail out due to savestating, the first thing we'll try afterwards is synchronize_cpu() again
synchronize_cpu();
switch(state) {
case State::Idle:
step(1);
break;
case State::DMA:
for(unsigned n = 0; n < regs.dma_length; n++) {
bus.write(regs.dma_target + n, bus.read(regs.dma_source + n));
step(2);
}
state = State::Idle;
break;
case State::Execute:
unsigned offset = regs.program_offset + regs.pc * 2;
opcode = bus_read(offset + 0) << 0;
opcode |= bus_read(offset + 1) << 8;
regs.pc = (regs.pc & 0xffff00) | ((regs.pc + 1) & 0x0000ff);
exec();
step(1);
break;
}
// this call is gone, but it's the first thing we try at the top of the loop AFTER we bail out
//synchronize_cpu();
}
}
TEST_F(WiegandReaderTest, readCard)
{
for (int i = 0; i < 32; i++)
{
high_.interrupt(); // building card id ff:ff:ff:ff
}
ASSERT_TRUE(bus_read(bus_sub_, "S_WIEGAND_1",
Leosac::Auth::SourceType::SIMPLE_WIEGAND, "ff:ff:ff:ff", 32));
for (int i = 0; i < 32; i++)
{
if (i >= 24)
high_.interrupt();
else
low_.interrupt();
//required because zmq sockets do fair-queuing.
// its not a problem either, because the hardware will pause too.
std::this_thread::sleep_for(std::chrono::milliseconds(2));
}
ASSERT_TRUE(bus_read(bus_sub_, "S_WIEGAND_1",
Leosac::Auth::SourceType::SIMPLE_WIEGAND, "00:00:00:ff", 32));
}
void arm_user_mode_init(generic_arch_t * arch_instance)
{
sky_pref_t *pref = get_skyeye_pref();
if (pref->user_mode_sim)
{
sky_exec_info_t *info = get_skyeye_exec_info();
info->arch_page_size = 0x1000;
info->arch_stack_top = 0x1ffffff0;// + 0x401fe7 - 0xff0; /* arbitrary value */
/* stack initial address specific to architecture may be placed here */
/* we need to mmap the stack space, if we are using skyeye space */
if (info->mmap_access)
{
/* get system stack size */
size_t stacksize = 0;
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_attr_getstacksize(&attr, &stacksize);
if (stacksize > info->arch_stack_top)
{
printf("arch_stack_top is too low\n");
stacksize = info->arch_stack_top;
}
/* Note: Skyeye is occupating 0x400000 to 0x600000 */
/* We do a mmap */
void* ret = mmap( (info->arch_stack_top) - stacksize,
stacksize + 0x1000 , PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
if (ret == MAP_FAILED){
/* ideally, we should find an empty space until it works */
printf("mmap error, stack couldn't be mapped: errno %d\n", errno);
exit(-1);
} else {
memset(ret, '\0', stacksize);
//printf("stack top has been defined at %x size %x\n", (uint32_t) ret + stacksize, stacksize);
//info->arch_stack_top = (uint32_t) ret + stacksize;
}
}
exec_stack_init();
ARM_CPU_State* cpu = get_current_cpu();
arm_core_t* core = &cpu->core[0];
uint32_t sp = info->initial_sp;
core->Cpsr = 0x10; /* User mode */
/* FIXME: may need to add thumb */
core->Reg[13] = sp;
core->Reg[10] = info->start_data;
core->Reg[0] = 0;
bus_read(32, sp + 4, &(core->Reg[1]));
bus_read(32, sp + 8, &(core->Reg[2]));
}
}
void fake_master::run()
{
uint32_t data = 0;
uint32_t addr = 0;
uint32_t length = 4;
bus_write(data, addr, 4);
wait(200, SC_NS);
addr += 4;
data += 100;
bus_write(data, addr, 4);
wait(200, SC_NS);
addr += 4;
data += 100;
bus_write(data, addr, 4);
wait(200, SC_NS);
addr += 4;
data += 100;
bus_write(data, addr, 4);
wait(200, SC_NS);
addr += 4;
data += 100;
bus_write(data, addr, 4);
wait(200, SC_NS);
addr = 0;
bus_read(&data, addr, 4);
wait(200, SC_NS);
addr += 4;
bus_read(&data, addr, 4);
wait(200, SC_NS);
addr += 4;
bus_read(&data, addr, 4);
wait(200, SC_NS);
addr += 4;
bus_read(&data, addr, 4);
wait(200, SC_NS);
addr += 4;
bus_read(&data, addr, 4);
wait(200, SC_NS);
}
int ppc_read_effective_byte(uint32 addr, uint8 *result)
{
e500_core_t * current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
uint32 p;
int r;
if (!(r = ppc_effective_to_physical(current_core, addr, PPC_MMU_READ, &p))) {
//ppc_io_read_byte (¤t_core-> p);
//printf("\nDBG:in %s,addr=0x%x,p=0x%x\n", __FUNCTION__, addr,p);
//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",current_core->ccsr.ccsr,GET_CCSR_BASE(current_core->ccsr.ccsr));
if(in_ccsr_range(p)){
int offset = p - current_core->get_ccsr_base(cpu->ccsr);
skyeye_config_t* config = get_current_config();
*result = config->mach->mach_io_read_byte(cpu, offset);
//*result = skyeye_config.mach->mach_io_read_byte(&gCPU, offset);
//printf("In %s, offset=0x%x, *result=0x%x\n", __FUNCTION__, offset, *result);
return r;
}
else{
if(bus_read(8, p, result) != 0){
}
//fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, current_core->pc);
//skyeye_exit(-1);
}
}
return r;
}
static uint32_t arch_arm_read_memory(cpu_t *cpu, addr_t addr,uint32_t size)
{
uint32_t value;
bus_read(size, (int)addr, &value);
return value;
}
int perform_read(const char *dev, uint32_t addr, int len)
{
struct dtree_dev_t *d = dtree_byname(dev);
if(d == NULL) {
fprintf(stderr, "No device '%s' found\n", dev);
return 1;
}
dtree_addr_t base = dtree_dev_base(d);
dtree_addr_t high = dtree_dev_high(d);
if(base < high) {
if(base + addr + len > high) {
verbosity_printf(1, "Address is out of range of the device: 0x%08X (high: 0x%08X)", base + addr, high);
return 2;
}
}
verbosity_printf(1, "Action: read, device: '%s', offset: '0x%08X', len: '%d'", dev, addr, len);
uint32_t value = bus_read(base, addr, len);
printf("0x%08X\n", value);
dtree_dev_free(d);
return 0;
}
uint8 SuperFX::step()
{
regs.r[15] += step_length;
regs.pipeline = bus_read((regs.pbr << 16) + regs.r[15].data);
regs.sfr = regs.sfr & ~(SFR_ALT3);
return regs.pipeline;
}
u1_t _r(u2_t a)
{
u1_t d;
d = bus_read(a);
//printf("read @ %3x = 0x%02x\n", a, d);
//printf("read @ %3x = %02x %08x %08x %08x\n", a, d,
// GPIO_OUT(0) & G0_ADDR, GPIO_OUT(1) & G1_ADDR, GPIO_OUT(3) & G3_ADDR);
return d;
}
static int flash_sst39lvf160_read_byte(struct device_desc *dev, uint32_t addr, uint8_t *data)
{
struct machine_config *mc = (struct machine_config*)dev->mach;
/*global_mbp = bank_ptr(addr);
*data = real_read_byte(state, addr);
*/
bus_read(8, addr, data);
DEBUG("read_byte(addr:0x%08x, data:0x%x)\n", addr, *data);
return ADDR_HIT;
}
uint8_t ow_read_bit(void)
{
int8_t r;
bus_low();
_delay_us(T/6);
bus_release();
_delay_us(T/12);
r = bus_read();
_delay_us(T/12+T/6+T/2);
return r;
}
size_t Mtd::read(uint8_t *rxbuf, size_t len, uint32_t offset) {
size_t ret;
if (nullptr != cfg.hook_start_read)
cfg.hook_start_read(this);
ret = bus_read(rxbuf, len, offset);
if (nullptr != cfg.hook_stop_read)
cfg.hook_stop_read(this);
return ret;
}
static void per_cpu_step(e500_core_t * running_core){
uint32 real_addr;
e500_core_t *core = running_core;
/* sometimes, core->npc will changed by another core */
if(core->ipi_flag){
core->pc = core->npc;
core->ipi_flag = 0;
}
core->step++;
core->npc = core->pc + 4;
switch( ppc_effective_to_physical(core, core->pc, PPC_MMU_CODE, &real_addr))
{
case PPC_MMU_OK:
break;
/* we had TLB miss and need to jump to its handler */
case PPC_MMU_EXC:
goto exec_npc;
case PPC_MMU_FATAL:
/* TLB miss */
fprintf(stderr, "TLB missed at 0x%x\n", core->pc);
skyeye_exit(-1);
default:
/* TLB miss */
fprintf(stderr, "Something wrong during address translation at 0x%x\n", core->pc);
skyeye_exit(-1);
};
uint32 instr;
if(bus_read(32, real_addr, &instr) != 0){
/* some error handler */
}
//core->current_opc = ppc_word_from_BE(instr);
core->current_opc = instr;
ppc_exec_opc(core);
//debug_log(core);
exec_npc:
if(!ppc_divisor){
core->dec_io_do_cycle(core);
ppc_divisor = 0;
}
else
ppc_divisor--;
//core->pc = core->npc;
core->pc = gCPU.core[core->pir].npc;
core->pc = core->npc;
}
static void bus_read_string(char *buf, char *str){
int i = 0;
char tmp[1024];
while(1){
bus_read(8, str + i ,tmp + i);
if(tmp[i] != '\0'){
i++;
}else{
buf[i + 1] = '\0';
strcpy(buf, tmp);
break;
}
}
}
static int flash_sst39lvf160_read_word(struct device_desc *dev, uint32_t addr, uint32_t *data)
{
struct machine_config *mc = (struct machine_config*)dev->mach;
ARMul_State *state = (ARMul_State*)mc->state;
/*
global_mbp = bank_ptr(addr);
*data = real_read_word(state, addr);
*/
bus_read(32, addr, data);
DEBUG("read_word(addr:0x%08x, data:0x%x)\n", addr, *data);
return ADDR_HIT;
}
/* One Wire functions */
uint8_t ow_reset(void)
{
// Wait until the bus is high
bus_release();
while( !(OW_BUS_PIN & OW_BUS_PIN_MASK));
uint8_t r = 0;
bus_low();
_delay_us(10*T);
bus_release();
_delay_us(2*T);
r = !bus_read();
_delay_us(6*T);
return r;
}
static uint32_t arch_mips_read_memory(cpu_t *cpu, addr_t addr, uint32_t size)
{
uint32_t result;
uint32_t pa = addr;
/* if pa is located at kseg0 */
if(pa >= 0x80000000 && pa < 0xA0000000)
pa = pa & ~0x80000000;
/* if pa is located at kseg1 */
if(pa >= 0xa0000000 && pa < 0xC0000000)
pa = pa & ~0xE0000000;
bus_read(size, pa, &result);
return result;
}
/* read instruction from RAM within 32-bits ARM mode */
bool ARMV5::inst_arm_read(void)
{
int fault = FAULT_NONE;
uint32_t addr = 0;
bool cachable = true;
if ((rf.pc & B8(11)) != 0) {
printb(core_id, d_armv5, "instruction address is not word boundary aligned: 0x%X", rf.pc);
}
/* address translation */
if (mmu_enable) {
fault = vir2phy(rf.pc, &addr, CPSR_MODE(rf.cpsr), false, &cachable);
}
else {
addr = rf.pc;
fault = FAULT_NONE;
}
/* memory access */
if (fault == FAULT_NONE) {
if (icache_enable && cachable) {
if (!icache_read(rf.pc)) {
delay += CYC_ICACHE_MISS;
}
}
else {
delay += 2;
}
if (bus_read(&inst, addr, 4)) {
return true;
}
else {
fault = FAULT_EXTERNAL;
}
}
/* fault handler */
cp15.c5_ifsr = fault;
cp15.c6_far = rf.pc;
return false;
}
int FASTCALL ppc_read_effective_word(uint32 addr, uint32 *result)
{
e500_core_t* current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
uint32 p;
int r;
if (!(r = ppc_effective_to_physical(current_core, addr, PPC_MMU_READ, &p))) {
if(in_ccsr_range(p)){
skyeye_config_t *config = get_current_config();
*result = config->mach->mach_io_read_word(cpu, (p - current_core->get_ccsr_base(cpu->ccsr)));
}
else{
if(bus_read(32, p, result) != 0){
}
}
}
return r;
}
unsigned char ds1302_read(unsigned char addr)
{
unsigned char val;
addr|=1; //读操作，最低bit为1，
CLR_RST;
bus_nop;
CLR_CLK;
bus_nop;
SET_RST;
bus_nop;
bus_write(addr); /* 地址，命令 */
val = bus_read(); /* 读1Byte数据 */
SET_CLK;
bus_nop;
CLR_RST;
bus_nop;
return(val);
}
/* read memory by external modules */
void ARMV5::memRead(uint32_t* data, uint32_t vir, int size)
{
/* NOTE: don't use data_read() function directly, or it probably brings some bizarre side effects */
uint32_t phy = 0;
bool cache = true;
if (mmu_enable) {
vir2phy(vir, &phy, CPSR_MODE(rf.cpsr), false, &cache);
}
else {
phy = vir;
}
printm(core_id, d_armv5_gdb, "memRead, vir = 0x%X, phy = 0x%X", vir, phy);
bus_read(data, phy, size);
printd(core_id, d_armv5_gdb, "memRead return: 0x%X", *data);
}
/**
* Listen (in a loop, forever) for new message on a bus
*
* @param bus Bus information
* @param callback Function to call when a message is received, the
* input parameters will be the read message and
* `user_data` from `bus_read`'s parameter with the
* same name. The message must have been parsed or
* copied when `callback` returns as it may be over
* overridden after that time. `callback` should
* return either of the the values:
* * 0: stop listening
* * 1: continue listening
* * -1: an error has occurred
* However, the function [`bus_read`] will invoke
* `callback` with `message` set to `NULL`one time
* directly after it has started listening on the
* bus. This is to the the program now it can safely
* continue with any action that requires that the
* programs is listening on the bus.
* @param user_data Parameter passed to `callback`
* @param timeout The time the operation shall fail with errno set
* to `EAGAIN` if not completed, note that the callback
* function may or may not have been called
* @param clockid The ID of the clock the `timeout` is measured with,
* it most be a predictable clock
* @return 0 on success, -1 on error
*/
int bus_read_timed(const bus_t *bus, int (*callback)(const char *message, void *user_data),
void *user_data, const struct timespec *timeout, clockid_t clockid)
{
int r, state = 0, saved_errno;
struct timespec delta;
if (!timeout)
return bus_read(bus, callback, user_data);
DELTA;
if (release_semaphore_timed(bus, S, SEM_UNDO, &delta) == -1)
return -1;
t(r = callback(NULL, user_data));
if (!r) goto done;
for (;;) {
DELTA;
t(release_semaphore_timed(bus, Q, 0, &delta));
DELTA;
t(zero_semaphore_timed(bus, Q, 0, &delta));
t(r = callback(bus->message, user_data));
if (!r) goto done;
t(release_semaphore(bus, W, SEM_UNDO)); state++;
t(acquire_semaphore(bus, S, SEM_UNDO)); state++;
t(zero_semaphore(bus, S, 0));
#ifndef BUS_SEMAPHORES_ARE_SYNCHRONOUS_ME_HARDER
t(zero_semaphore(bus, N, 0));
#endif
t(release_semaphore(bus, S, SEM_UNDO)); state--;
t(acquire_semaphore(bus, W, SEM_UNDO)); state--;
}
fail:
saved_errno = errno;
if (state > 1)
release_semaphore(bus, S, SEM_UNDO);
if (state > 0)
acquire_semaphore(bus, W, SEM_UNDO);
acquire_semaphore(bus, S, SEM_UNDO);
errno = saved_errno;
return -1;
done:
t(acquire_semaphore(bus, S, SEM_UNDO));
return 0;
}
void ds1302_time_get_burst(unsigned char *val)
{
unsigned char i;
CLR_RST;
bus_nop;
CLR_CLK;
bus_nop;
SET_RST;
bus_nop;
bus_write(DS1302_CLKBURST_Reg+1); /* 0xbf:时钟多字节读命令 */
for (i=8; i>0; i--)
{
*val = bus_read(); /* 读1Byte数据 */
val++;
}
SET_CLK;
bus_nop;
CLR_RST;
}
void ds1302_ram_read_burst(unsigned char *val)
{
unsigned char i;
CLR_RST;
bus_nop;
CLR_CLK;
bus_nop;
SET_RST;
bus_nop;
DS1302_RAM_BURST_READ;/* 0xff:RAM字节读命令 */
for (i=31; i>0; i--) /*31Byte 寄存器数据 */
{
*val = bus_read(); /* 读1Byte数据 */
val++;
}
SET_CLK;
bus_nop;
CLR_RST;
}
int
main(int argc_, char *argv_[])
{
bus_t bus;
int i;
argc = argc_;
argv = argv_;
if (argc < 2)
return fprintf(stderr, "USAGE: %s daemon...", *argv), 2;
t(bus_open(&bus, getenv("BUS_INIT"), BUS_RDONLY));
started = calloc(argc, sizeof(char));
t(started == NULL);
started[0] = 1;
for (i = 1; i < argc; i++) {
sprintf(arg, "grep '^%s$' < \"${XDG_RUNTIME_DIR}/started-daemons\" >/dev/null", argv[i]);
if (!WEXITSTATUS(system(arg))) {
started[i] = 1;
} else {
sprintf(arg, "grep '^%s$' < \"${XDG_RUNTIME_DIR}/ready-daemons\" >/dev/null", argv[i]);
if (!WEXITSTATUS(system(arg)))
started[i] = 1;
else
remaining++;
}
}
if (remaining)
bus_read(&bus, callback, NULL);
bus_close(&bus);
free(started);
return 0;
fail:
perror("await-started");
bus_close(&bus);
free(started);
return 1;
}
u1_t handler_dev_display_read(u2_t addr)
{
u1_t data;
assert (addr == RREG_KEY_SCAN);
// For reasons that are not understood, when the -O3 optimized version of the app are run in
// auto-start mode the reset key push is not detected most of the time unless this delay is added.
// Oddly, this bug doesn't appear if the optimized version is run from the command line, which makes no sense.
// It doesn't appear to be code getting optimized away or a missing volatile declaration but rather timing related.
#ifndef DEBUG
delay(1);
#endif
data = bus_read(addr);
if (data != KEY_IDLE) {
process_key(data);
} else
if (sim_key) {
data = sim_key;
// simulate reset key down for an extended period
if (reset_key_down) {
if ((time_diff(timer_ms(), reset_key_down) > 1250)) reset_key_down = 0;
} else {
if (sim_running) {
if (!sim_key_intr) sim_key = 0; // allow it to be read twice, but generate interrupt only once
} else {
sim_key = 0; // only once for non-simulator uses
}
}
sim_key_intr = 0;
process_key(data);
}
return data;
}
int FASTCALL ppc_read_effective_half(uint32 addr, uint16 *result)
{
e500_core_t * current_core = get_current_core();
PPC_CPU_State* cpu = get_current_cpu();
uint32 p;
int r;
if (!(r = ppc_effective_to_physical(current_core, addr, PPC_MMU_READ, &p))) {
//ppc_io_read_halfword(¤t_core-> p);
//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",current_core->ccsr.ccsr,GET_CCSR_BASE(current_core->ccsr.ccsr));
if(in_ccsr_range(p)){
//*result = skyeye_config.mach->mach_io_read_halfword(&gCPU, (p - GET_CCSR_BASE(gCPU.ccsr)));
skyeye_config_t* config = get_current_config();
*result = config->mach->mach_io_read_halfword(cpu, (p - current_core->get_ccsr_base(cpu->ccsr)));
}
else{
if(bus_read(16, p, result) != 0){
}
//fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, current_core->pc);
//skyeye_exit(-1);
}
}
return r;
}
void input_refresh(void)
/* Reads one column of switch data each time it is called and auto-increments
the current row
*/
{
static uint8_t current_row = 0;
static uint8_t stage = 0;
static uint8_t last_data = 0;
// Update row latch value
bus_select(ROW_ADDRESS);
bus_write(row_mirror | (0x20 << current_row));
nop();
// Latch row value and switch to the switch column input buffer
bus_select(SWITCHCOL_ADDRESS);
bus_dir_input();
uint8_t switch_data = bus_read();
bus_dir_output();
bus_deselect();
if (stage == 1) {
// Expand the switch bits into individual bytes in the input array
uint8_t* row = &input[current_row];
// Debouncing:
*row = (switch_data & *row) | (switch_data & last_data) | (last_data & *row);
if (++current_row == 3)
current_row = 0;
}
stage ^= 1;
last_data = switch_data;
}
/*!
* Starts running the processor with the current contents of the instruction
* store and the register file. The function terminates when the processor hits
* the ALUOP_DONE instruction.
*/
void run(Processor *proc) {
int t;
printf("Running processor.\n\n");
printf("T=0\tRegister File: ");
rfprint(stdout, proc->rf);
/* Since we have branching, we can't just run until we hit the instruction
* store depth. Instead, we set a "max execute time," beyond which we
* assume that the program has an infinite loop in it.
*/
for (t = 1; t < MAX_EXECUTE_TIME; t++) {
clock(proc);
printf("\nT=%d\tPC=%d\tALUOP=%X\tW=%X\tSRC1=%X\tSRC2=%X\tDST=%X\tBRA=%X\n"
"\tRF1=%X\tRF2=%X\tALUOUT=%X\tBR?=%X\n",
t,
bus_read(proc->pc_bus) - 1,
bus_read(proc->aluop),
bus_read(proc->writep),
bus_read(proc->src1),
bus_read(proc->src2),
bus_read(proc->dst),
bus_read(proc->branch_addr),
bus_read(proc->rf1),
bus_read(proc->rf2),
bus_read(proc->aluout),
bus_read(proc->branch)
);
printf("\n\tRegister File: ");
rfprint(stdout, proc->rf);
if (bus_read(proc->aluop) == ALUOP_DONE)
break;
}
printf("\n");
if (t == MAX_EXECUTE_TIME) {
printf("ERROR: Max execute time reached.\n"
"Does your program have an infinite loop in it?\n");
}
else {
printf("Program terminated normally.\n");
}
}
void meas_extend_example(u1_t key)
{
int i;
u4_t n0st, n0st2, n1n2h, n1n2l, n0h, n0l;
s4_t n1n2, n0;
double ti;
printf("measurement extension example called\n");
dsp_7seg_str(POS(2), "extend", DSP_CLEAR);
if (key & KEY(LCL_RMT)) {
printf("LCL/RMT\n");
}
#define N_TI 100000
printf("taking %d TI measurements\n", N_TI);
for (i=0; i<N_TI; i++) {
bus_write(WREG_O3, WREG_O3_RST);
bus_write(WREG_O2, WREG_O2_ENA);
bus_write(WREG_O2, WREG_O2_ARM);
// wait for end-of-measurement
do {
n0st = bus_read(RREG_N0ST);
} while (isInactive(N0ST_EOM, n0st));
bus_write(WREG_O2, WREG_O2_IDLE);
n0st = bus_read(RREG_N0ST);
n1n2h = bus_read(RREG_N1N2H);
n1n2l = bus_read(RREG_N1N2L);
n1n2 = ((n0st & N0ST_N1N2) << 16) | (n1n2h << 8) | n1n2l;
if (isActive(N0ST_PLL_OOL, n0st)) printf("PLL UNLOCKED\n");
if (isActive(N0ST_N0_OVFL, n0st)) printf("N0 OVFL\n");
// convert from 18-bit 2s complement
if (n1n2 >= 0x20000) {
n1n2 = n1n2 - 0x40000;
}
n0h = bus_read(RREG_N0H);
n0l = bus_read(RREG_N0L);
n0 = (n0h << 8) | n0l;
// convert from 16-bit sign-magnitude
if ((n0st & N0ST_N0_POS) == 0) {
n0 = -n0;
}
ti = (((double) n1n2 / 256.0) + (double) n0) * 5.0e-9;
bool rng = ((ti < 98.0e-9) || (ti > 101.1e+9))? TRUE:FALSE;
if (rng) {
printf("meas %d, N0ST 0x%02x, out of range: ", i, n0st & N0ST_STATUS);
if (ti < 1.0e-8) {
printf("%1.2f ns\n", ti * 1.0e8);
} else {
printf("%2.2f ns\n", ti * 1.0e9);
}
}
}
wait_key_release();
printf("measurement extension example returning\n");
dsp_7seg_str(DSP_LEFT, "", DSP_CLEAR);
}