int
ichsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
{
const sc_p sc = device_get_softc(dev);
int smb_error;
DBG("slave=0x%02x cmd=0x%02x sdata=0x%04x\n",
slave, (u_char)cmd, (u_int16_t)sdata);
KASSERT(sc->ich_cmd == -1,
("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
mtx_lock(&sc->mutex);
sc->ich_cmd = ICH_HST_CNT_SMB_CMD_PROC_CALL;
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
slave | ICH_XMIT_SLVA_WRITE);
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_D0, sdata & 0xff);
bus_write_1(sc->io_res, ICH_D1, sdata >> 8);
bus_write_1(sc->io_res, ICH_HST_CNT,
ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
*rdata = (bus_read_1(sc->io_res,
ICH_D0) & 0xff)
| (bus_read_1(sc->io_res,
ICH_D1) << 8);
}
mtx_unlock(&sc->mutex);
DBG("smb_error=%d rdata=0x%04x\n", smb_error, (u_int16_t)*rdata);
return (smb_error);
}
/*
* Polling Code.
*
* Polling is not encouraged because it requires waiting for the
* device if it is busy.
* (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
* polling code then.
*/
static int
intsmb_stop_poll(struct intsmb_softc *sc)
{
int error, i, status, tmp;
INTSMB_LOCK_ASSERT(sc);
/* First, wait for busy to be set. */
for (i = 0; i < 0x7fff; i++)
if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
PIIX4_SMBHSTSTAT_BUSY)
break;
/* Wait for busy to clear. */
for (i = 0; i < 0x7fff; i++) {
status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
sc->isbusy = 0;
error = intsmb_error(sc->dev, status);
return (error);
}
}
/* Timed out waiting for busy to clear. */
sc->isbusy = 0;
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
return (SMB_ETIMEOUT);
}
static int
intsmb_recvb(device_t dev, u_char slave, char *byte)
{
struct intsmb_softc *sc = device_get_softc(dev);
int error;
INTSMB_LOCK(sc);
error = intsmb_free(sc);
if (error) {
INTSMB_UNLOCK(sc);
return (error);
}
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
error = intsmb_stop(sc);
if (error == 0) {
#ifdef RECV_IS_IN_CMD
/*
* Linux SMBus stuff also troubles
* Because Intel's datasheet does not make clear.
*/
*byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
#else
*byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
#endif
}
INTSMB_UNLOCK(sc);
return (error);
}
int
ichsmb_readw(device_t dev, u_char slave, char cmd, short *word)
{
const sc_p sc = device_get_softc(dev);
int smb_error;
DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
KASSERT(sc->ich_cmd == -1,
("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
mtx_lock(&sc->mutex);
sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
bus_write_1(sc->io_res, ICH_XMIT_SLVA,
slave | ICH_XMIT_SLVA_READ);
bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
bus_write_1(sc->io_res, ICH_HST_CNT,
ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
*word = (bus_read_1(sc->io_res,
ICH_D0) & 0xff)
| (bus_read_1(sc->io_res,
ICH_D1) << 8);
}
mtx_unlock(&sc->mutex);
DBG("smb_error=%d word=0x%04x\n", smb_error, (u_int16_t)*word);
return (smb_error);
}
static int
intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
{
struct intsmb_softc *sc = device_get_softc(dev);
int error, i;
u_char data, nread;
INTSMB_LOCK(sc);
error = intsmb_free(sc);
if (error) {
INTSMB_UNLOCK(sc);
return (error);
}
/* Reset internal array index. */
bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
error = intsmb_stop(sc);
if (error == 0) {
nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
*count = nread;
for (i = 0; i < nread; i++)
data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
} else
error = SMB_EBUSERR;
}
INTSMB_UNLOCK(sc);
return (error);
}
void
gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
{
int i;
GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
if (ctx->istatus & 0x80) { /* error flag */
ctx->istatus &= ~0x80;
ctx->cmd_status = bus_read_2(gdt->sc_dpmem, GDT_MPR_STATUS);
} else /* no error */
ctx->cmd_status = GDT_S_OK;
ctx->info = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO);
ctx->service = bus_read_2(gdt->sc_dpmem, GDT_MPR_SERVICE);
ctx->info2 = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO + sizeof (u_int32_t));
/* event string */
if (ctx->istatus == GDT_ASYNCINDEX) {
if (ctx->service != GDT_SCREENSERVICE &&
(gdt->sc_fw_vers & 0xff) >= 0x1a) {
gdt->sc_dvr.severity = bus_read_1(gdt->sc_dpmem, GDT_SEVERITY);
for (i = 0; i < 256; ++i) {
gdt->sc_dvr.event_string[i] = bus_read_1(gdt->sc_dpmem,
GDT_EVT_BUF + i);
if (gdt->sc_dvr.event_string[i] == 0)
break;
}
}
}
bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA1, 0);
}
/*
* Data sheet claims that it implements all function, but also claims
* that it implements 7 function and not mention PCALL. So I don't know
* whether it will work.
*/
static int
intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
{
#ifdef PROCCALL_TEST
struct intsmb_softc *sc = device_get_softc(dev);
int error;
INTSMB_LOCK(sc);
error = intsmb_free(sc);
if (error) {
INTSMB_UNLOCK(sc);
return (error);
}
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, sdata & 0xff);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (sdata & 0xff) >> 8);
intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
error = intsmb_stop(sc);
if (error == 0) {
*rdata = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
*rdata |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
}
INTSMB_UNLOCK(sc);
return (error);
#else
return (SMB_ENOTSUPP);
#endif
}
/*
* Read the CIS data out of memroy. We indirect through the bus space
* routines to ensure proper byte ordering conversions when necessary.
*/
static int
cardbus_read_tuple_mem(device_t cbdev, struct resource *res, uint32_t start,
uint32_t *off, int *tupleid, int *len, uint8_t *tupledata)
{
int ret;
*tupleid = bus_read_1(res, start + *off);
*len = bus_read_1(res, start + *off + 1);
bus_read_region_1(res, *off + start + 2, tupledata, *len);
ret = 0;
*off += *len + 2;
return (ret);
}
static int
intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
{
struct intsmb_softc *sc = device_get_softc(dev);
int error, i;
if (count > SMBBLOCKTRANS_MAX || count == 0)
return (SMB_EINVAL);
INTSMB_LOCK(sc);
error = intsmb_free(sc);
if (error) {
INTSMB_UNLOCK(sc);
return (error);
}
/* Reset internal array index. */
bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
for (i = 0; i < count; i++)
bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
error = intsmb_stop(sc);
INTSMB_UNLOCK(sc);
return (error);
}
static int
nsp_expect_signal(struct nsp_softc *sc, u_int8_t curphase, u_int8_t mask)
{
struct scsi_low_softc *slp = &sc->sc_sclow;
int wc;
u_int8_t ph, isrc;
for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++)
{
ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
if (ph == (u_int8_t) -1)
return -1;
isrc = bus_read_1(sc->port_res, nsp_irqsr);
if (isrc & IRQSR_SCSI)
return 0;
if ((ph & mask) != 0 && (ph & SCBUSMON_PHMASK) == curphase)
return 1;
DELAY(NSP_DELAY_INTERVAL);
}
device_printf(slp->sl_dev, "nsp_expect_signal timeout\n");
return -1;
}
/****************************************************
* hwfuncs
****************************************************/
static __inline uint8_t
nsp_cr_read_1(struct resource *res, bus_addr_t ofs)
{
bus_write_1(res, nsp_idxr, ofs);
return bus_read_1(res, nsp_datar);
}
/*
* Wait for command completion. Assumes mutex is held.
* Returns an SMB_* error code.
*/
static int
ichsmb_wait(sc_p sc)
{
const device_t dev = sc->dev;
int error, smb_error;
KASSERT(sc->ich_cmd != -1,
("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
mtx_assert(&sc->mutex, MA_OWNED);
error = msleep(sc, &sc->mutex, PZERO, "ichsmb", hz / 4);
DBG("msleep -> %d\n", error);
switch (error) {
case 0:
smb_error = sc->smb_error;
break;
case EWOULDBLOCK:
device_printf(dev, "device timeout, status=0x%02x\n",
bus_read_1(sc->io_res, ICH_HST_STA));
sc->ich_cmd = -1;
smb_error = SMB_ETIMEOUT;
break;
default:
smb_error = SMB_EABORT;
break;
}
return (smb_error);
}
/**
* Read a data item from the bridged address space at the given @p offset
* from @p addr.
*
* A dynamic register window will be used to map @p addr.
*
* @param probe The bhndb_pci probe state to be used to perform the
* read.
* @param addr The base address.
* @param offset The offset from @p addr at which to read a data item of
* @p width bytes.
* @param width Item width (1, 2, or 4 bytes).
*/
static uint32_t
bhndb_pci_probe_read(struct bhndb_pci_probe *probe, bhnd_addr_t addr,
bhnd_size_t offset, u_int width)
{
struct resource *r;
bus_size_t res_offset;
int error;
/* Map the target address */
error = bhndb_pci_probe_map(probe, addr, offset, width, &r,
&res_offset);
if (error) {
device_printf(probe->dev, "error mapping %#jx+%#jx for "
"reading: %d\n", addr, offset, error);
return (UINT32_MAX);
}
/* Perform read */
switch (width) {
case 1:
return (bus_read_1(r, res_offset));
case 2:
return (bus_read_2(r, res_offset));
case 4:
return (bus_read_4(r, res_offset));
default:
panic("unsupported width: %u", width);
}
}
u_int8_t
gdt_mpr_get_status(struct gdt_softc *gdt)
{
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
return bus_read_1(gdt->sc_dpmem, GDT_MPR_EDOOR);
}
int
gdt_mpr_test_busy(struct gdt_softc *gdt)
{
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
return (bus_read_1(gdt->sc_dpmem, GDT_MPR_SEMA0) & 1);
}
static __inline uint8_t
atpic_read(struct atpic_softc *sc, int icu, int ofs)
{
uint8_t val;
val = bus_read_1(sc->sc_res[icu], ofs);
return (val);
}
static int
macgpio_suspend(device_t dev)
{
struct macgpio_softc *sc;
int i;
sc = device_get_softc(dev);
sc->sc_saved_gpio_levels[0] = bus_read_4(sc->sc_gpios, GPIO_LEVELS_0);
sc->sc_saved_gpio_levels[1] = bus_read_4(sc->sc_gpios, GPIO_LEVELS_1);
for (i = 0; i < GPIO_COUNT; i++)
sc->sc_saved_gpios[i] = bus_read_1(sc->sc_gpios, GPIO_BASE + i);
for (i = 0; i < GPIO_EXTINT_COUNT; i++)
sc->sc_saved_extint_gpios[i] = bus_read_1(sc->sc_gpios, GPIO_EXTINT_BASE + i);
return (0);
}
static int
iicoc_dev_read(device_t dev, int reg)
{
uint8_t val;
struct iicoc_softc *sc;
sc = device_get_softc(dev);
val = bus_read_1(sc->mem_res, reg<<sc->reg_shift);
return (val);
}
static int
proto_read(struct cdev *cdev, struct uio *uio, int ioflag)
{
union {
uint8_t x1[8];
uint16_t x2[4];
uint32_t x4[2];
uint64_t x8[1];
} buf;
struct proto_softc *sc;
struct proto_res *r;
device_t dev;
off_t ofs;
u_long width;
int error;
sc = cdev->si_drv1;
dev = sc->sc_dev;
r = cdev->si_drv2;
width = uio->uio_resid;
if (width < 1 || width > 8 || bitcount16(width) > 1)
return (EIO);
ofs = uio->uio_offset;
if (ofs + width > r->r_size)
return (EIO);
switch (width) {
case 1:
buf.x1[0] = (r->r_type == PROTO_RES_PCICFG) ?
pci_read_config(dev, ofs, 1) : bus_read_1(r->r_d.res, ofs);
break;
case 2:
buf.x2[0] = (r->r_type == PROTO_RES_PCICFG) ?
pci_read_config(dev, ofs, 2) : bus_read_2(r->r_d.res, ofs);
break;
case 4:
buf.x4[0] = (r->r_type == PROTO_RES_PCICFG) ?
pci_read_config(dev, ofs, 4) : bus_read_4(r->r_d.res, ofs);
break;
#ifndef __i386__
case 8:
if (r->r_type == PROTO_RES_PCICFG)
return (EINVAL);
buf.x8[0] = bus_read_8(r->r_d.res, ofs);
break;
#endif
default:
return (EIO);
}
error = uiomove(&buf, width, uio);
return (error);
}
static int
pcii_probe(device_t dev)
{
int rid, i, j;
u_long start, count;
int error = 0;
struct pcii_softc *sc;
device_set_desc(dev, "PCII IEEE-4888 controller");
sc = device_get_softc(dev);
rid = 0;
if (bus_get_resource(dev, SYS_RES_IOPORT, rid, &start, &count) != 0)
return ENXIO;
if ((start & 0x3ff) != 0x2e1)
return (ENXIO);
count = 1;
if (bus_set_resource(dev, SYS_RES_IOPORT, rid, start, count) != 0)
return ENXIO;
error = bus_alloc_resources(dev, pcii_res_spec, sc->res);
if (error)
return (error);
error = ENXIO;
for (i = 0; i < 8; i++) {
j = bus_read_1(sc->res[2], i * 0x400);
if (j != 0x00 && j != 0xff)
error = 0;
}
if (!error) {
bus_write_1(sc->res[2], 3 * 0x400, 0x55);
if (bus_read_1(sc->res[2], 3 * 0x400) != 0x55)
error = ENXIO;
}
if (!error) {
bus_write_1(sc->res[2], 3 * 0x400, 0xaa);
if (bus_read_1(sc->res[2], 3 * 0x400) != 0xaa)
error = ENXIO;
}
bus_release_resources(dev, pcii_res_spec, sc->res);
return (error);
}
static void
le_lebuffer_copyfrombuf(struct lance_softc *sc, void *tov, int off, int len)
{
struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc;
caddr_t to = tov;
for (; len >= 2; len -= 2, off += 2, to += 2)
le16enc(to,
bus_read_2(lesc->sc_bres, off));
if (len == 1)
*to = bus_read_1(lesc->sc_bres, off + 1);
}
static uint8_t
rb_nand_read_byte(device_t dev)
{
struct rb_nand_softc *sc;
uint8_t data;
sc = device_get_softc(dev);
data = bus_read_1(sc->sc_mem, RB_NAND_DATA);
nand_debug(NDBG_DRV,"rb_nand: read %x", data);
return (data);
}
/* Enable interrupts */
void
gdt_pci_enable_intr(struct gdt_softc *gdt)
{
GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
switch(GDT_CLASS(gdt)) {
case GDT_MPR:
bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
bus_write_1(gdt->sc_dpmem, GDT_EDOOR_EN,
bus_read_1(gdt->sc_dpmem, GDT_EDOOR_EN) & ~4);
break;
}
}
static void
intsmb_alrintr(struct intsmb_softc *sc)
{
int slvcnt;
#ifdef ENABLE_ALART
int error;
uint8_t addr;
#endif
/* Stop generating INTR from ALART. */
slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
#ifdef ENABLE_ALART
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
#endif
DELAY(5);
/* Ask bus who asserted it and then ask it what's the matter. */
#ifdef ENABLE_ALART
error = intsmb_free(sc);
if (error)
return;
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
error = intsmb_stop_poll(sc);
if (error)
device_printf(sc->dev, "ALART: ERROR\n");
else {
addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
}
/* Re-enable INTR from ALART. */
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
slvcnt | PIIX4_SMBSLVCNT_ALTEN);
DELAY(5);
#endif
}
uint8_t
macgpio_read(device_t dev)
{
struct macgpio_softc *sc;
struct macgpio_devinfo *dinfo;
sc = device_get_softc(device_get_parent(dev));
dinfo = device_get_ivars(dev);
if (dinfo->gpio_num < 0)
return (0);
return (bus_read_1(sc->sc_gpios,dinfo->gpio_num));
}
static int
intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
{
struct intsmb_softc *sc = device_get_softc(dev);
int error;
INTSMB_LOCK(sc);
error = intsmb_free(sc);
if (error) {
INTSMB_UNLOCK(sc);
return (error);
}
bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
error = intsmb_stop(sc);
if (error == 0) {
*word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
*word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
}
INTSMB_UNLOCK(sc);
return (error);
}
/* Counterpart of smbtx_smb_free(). */
static int
intsmb_free(struct intsmb_softc *sc)
{
INTSMB_LOCK_ASSERT(sc);
if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
#ifdef ENABLE_ALART
(bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
#endif
sc->isbusy)
return (SMB_EBUSY);
sc->isbusy = 1;
/* Disable Interrupt in slave part. */
#ifndef ENABLE_ALART
bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
#endif
/* Reset INTR Flag to prepare INTR. */
bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
return (0);
}
static int
intsmb_intr(struct intsmb_softc *sc)
{
int status, tmp;
status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
if (status & PIIX4_SMBHSTSTAT_BUSY)
return (1);
if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
tmp & ~PIIX4_SMBHSTCNT_INTREN);
if (sc->isbusy) {
sc->isbusy = 0;
wakeup(sc);
}
return (0);
}
return (1); /* Not Completed */
}
static u_char
esp_read_reg(struct ncr53c9x_softc *sc, int reg)
{
struct esp_softc *esc = (struct esp_softc *)sc;
u_char v;
v = bus_read_1(esc->sc_res, reg * 4);
#ifdef ESP_SBUS_DEBUG
if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
printf("RD:%x <%s> %x\n", reg * 4, ((unsigned)reg < 0x10) ?
esp__read_regnames[reg].r_name : "<***>", v);
#endif
return (v);
}
static void
intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
{
unsigned char tmp;
INTSMB_LOCK_ASSERT(sc);
tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
tmp &= 0xe0;
tmp |= cmd;
tmp |= PIIX4_SMBHSTCNT_START;
/* While not in autoconfiguration enable interrupts. */
if (!sc->poll && !cold && !nointr)
tmp |= PIIX4_SMBHSTCNT_INTREN;
bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
}
