void
gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
{
int i;
GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
bus_write_1(gdt->sc_dpmem, GDT_MPR_EDOOR, 0xff);
if (ctx->istatus & 0x80) { /* error flag */
ctx->istatus &= ~0x80;
ctx->cmd_status = bus_read_2(gdt->sc_dpmem, GDT_MPR_STATUS);
} else /* no error */
ctx->cmd_status = GDT_S_OK;
ctx->info = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO);
ctx->service = bus_read_2(gdt->sc_dpmem, GDT_MPR_SERVICE);
ctx->info2 = bus_read_4(gdt->sc_dpmem, GDT_MPR_INFO + sizeof (u_int32_t));
/* event string */
if (ctx->istatus == GDT_ASYNCINDEX) {
if (ctx->service != GDT_SCREENSERVICE &&
(gdt->sc_fw_vers & 0xff) >= 0x1a) {
gdt->sc_dvr.severity = bus_read_1(gdt->sc_dpmem, GDT_SEVERITY);
for (i = 0; i < 256; ++i) {
gdt->sc_dvr.event_string[i] = bus_read_1(gdt->sc_dpmem,
GDT_EVT_BUF + i);
if (gdt->sc_dvr.event_string[i] == 0)
break;
}
}
}
bus_write_1(gdt->sc_dpmem, GDT_MPR_SEMA1, 0);
}
/* Never call this when not in bank 2. */
static __inline void
smc_mmu_wait(struct smc_softc *sc)
{
KASSERT((bus_read_2(sc->smc_reg, BSR) &
BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
device_get_nameunit(sc->smc_dev)));
while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
;
}
static uint64_t
isf_read_reg64(struct isf_softc *sc, uint16_t reg)
{
uint64_t val;
uint16_t *val16 = (uint16_t *)&val;
if (isf_debug)
device_printf(sc->isf_dev, "isf_read_reg64(0x%02x)\n", reg);
val16[0] = bus_read_2(sc->isf_res, reg * 2);
val16[1] = bus_read_2(sc->isf_res, (reg+1) * 2);
val16[2] = bus_read_2(sc->isf_res, (reg+2) * 2);
val16[3] = bus_read_2(sc->isf_res, (reg+3) * 2);
return(le64toh(val));
}
/**
* Read a data item from the bridged address space at the given @p offset
* from @p addr.
*
* A dynamic register window will be used to map @p addr.
*
* @param probe The bhndb_pci probe state to be used to perform the
* read.
* @param addr The base address.
* @param offset The offset from @p addr at which to read a data item of
* @p width bytes.
* @param width Item width (1, 2, or 4 bytes).
*/
static uint32_t
bhndb_pci_probe_read(struct bhndb_pci_probe *probe, bhnd_addr_t addr,
bhnd_size_t offset, u_int width)
{
struct resource *r;
bus_size_t res_offset;
int error;
/* Map the target address */
error = bhndb_pci_probe_map(probe, addr, offset, width, &r,
&res_offset);
if (error) {
device_printf(probe->dev, "error mapping %#jx+%#jx for "
"reading: %d\n", addr, offset, error);
return (UINT32_MAX);
}
/* Perform read */
switch (width) {
case 1:
return (bus_read_1(r, res_offset));
case 2:
return (bus_read_2(r, res_offset));
case 4:
return (bus_read_4(r, res_offset));
default:
panic("unsupported width: %u", width);
}
}
static void
imx_ata_intr(void *data)
{
struct ata_pci_controller *ctrl = data;
bus_write_2(ctrl->r_res1, 0x28, bus_read_2(ctrl->r_res1, 0x28));
ctrl->interrupt[0].function(ctrl->interrupt[0].argument);
}
static uint16_t
isf_read_reg(struct isf_softc *sc, uint16_t reg)
{
if (isf_debug)
device_printf(sc->isf_dev, "isf_read_reg(0x%02x)\n", reg);
return (le16toh(bus_read_2(sc->isf_res, reg * 2)));
}
static uint16_t
le_lebuffer_rdcsr(struct lance_softc *sc, uint16_t port)
{
struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc;
bus_write_2(lesc->sc_rres, LEREG1_RAP, port);
bus_barrier(lesc->sc_rres, LEREG1_RAP, 2, BUS_SPACE_BARRIER_WRITE);
return (bus_read_2(lesc->sc_rres, LEREG1_RDP));
}
static uint16_t
le_pci_rdbcr(struct lance_softc *sc, uint16_t port)
{
struct le_pci_softc *lesc = (struct le_pci_softc *)sc;
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port);
bus_barrier(lesc->sc_rres, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE);
return (bus_read_2(lesc->sc_rres, PCNET_PCI_BDP));
}
static uint16_t
le_isa_rdcsr(struct lance_softc *sc, uint16_t port)
{
struct le_isa_softc *lesc = (struct le_isa_softc *)sc;
bus_write_2(lesc->sc_rres, lesc->sc_rap, port);
bus_barrier(lesc->sc_rres, lesc->sc_rap, 2, BUS_SPACE_BARRIER_WRITE);
return (bus_read_2(lesc->sc_rres, lesc->sc_rdp));
}
static int
proto_read(struct cdev *cdev, struct uio *uio, int ioflag)
{
union {
uint8_t x1[8];
uint16_t x2[4];
uint32_t x4[2];
uint64_t x8[1];
} buf;
struct proto_softc *sc;
struct proto_res *r;
device_t dev;
off_t ofs;
u_long width;
int error;
sc = cdev->si_drv1;
dev = sc->sc_dev;
r = cdev->si_drv2;
width = uio->uio_resid;
if (width < 1 || width > 8 || bitcount16(width) > 1)
return (EIO);
ofs = uio->uio_offset;
if (ofs + width > r->r_size)
return (EIO);
switch (width) {
case 1:
buf.x1[0] = (r->r_type == PROTO_RES_PCICFG) ?
pci_read_config(dev, ofs, 1) : bus_read_1(r->r_d.res, ofs);
break;
case 2:
buf.x2[0] = (r->r_type == PROTO_RES_PCICFG) ?
pci_read_config(dev, ofs, 2) : bus_read_2(r->r_d.res, ofs);
break;
case 4:
buf.x4[0] = (r->r_type == PROTO_RES_PCICFG) ?
pci_read_config(dev, ofs, 4) : bus_read_4(r->r_d.res, ofs);
break;
#ifndef __i386__
case 8:
if (r->r_type == PROTO_RES_PCICFG)
return (EINVAL);
buf.x8[0] = bus_read_8(r->r_d.res, ofs);
break;
#endif
default:
return (EIO);
}
error = uiomove(&buf, width, uio);
return (error);
}
static void
le_lebuffer_copyfrombuf(struct lance_softc *sc, void *tov, int off, int len)
{
struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc;
caddr_t to = tov;
for (; len >= 2; len -= 2, off += 2, to += 2)
le16enc(to,
bus_read_2(lesc->sc_bres, off));
if (len == 1)
*to = bus_read_1(lesc->sc_bres, off + 1);
}
static uint16_t
le_pci_rdcsr(struct lance_softc *sc, uint16_t port)
{
struct le_pci_softc *lesc = (struct le_pci_softc *)sc;
#ifdef __HAIKU__
HAIKU_INTR_REGISTER_STATE;
uint16_t value;
if (port == LE_CSR0)
HAIKU_INTR_REGISTER_ENTER();
#endif
bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port);
bus_barrier(lesc->sc_rres, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE);
#ifndef __HAIKU__
return (bus_read_2(lesc->sc_rres, PCNET_PCI_RDP));
#else
value = bus_read_2(lesc->sc_rres, PCNET_PCI_RDP);
if (port == LE_CSR0)
HAIKU_INTR_REGISTER_LEAVE();
return value;
#endif
}
static uint16_t
isf_read_off(struct isf_softc *sc, off_t off)
{
KASSERT(off >= 0, ("%s: negative offset\n", __func__));
KASSERT(off < sc->isf_disk->d_mediasize,
("%s: offset out side address space 0x%08jx \n", __func__,
(intmax_t)off));
if (isf_debug)
device_printf(sc->isf_dev, "isf_read_off(0x%08jx)\n",
(intmax_t)off);
return (le16toh(bus_read_2(sc->isf_res, off)));
}
static void
le_lebuffer_copyfromdesc(struct lance_softc *sc, void *tov, int off, int len)
{
struct le_lebuffer_softc *lesc = (struct le_lebuffer_softc *)sc;
caddr_t to = tov;
for (; len >= 8; len -= 8, off += 8, to += 8)
be64enc(to,
bus_read_8(lesc->sc_bres, off));
for (; len >= 4; len -= 4, off += 4, to += 4)
be32enc(to,
bus_read_4(lesc->sc_bres, off));
for (; len >= 2; len -= 2, off += 2, to += 2)
be16enc(to,
bus_read_2(lesc->sc_bres, off));
if (len == 1)
*to = bus_read_1(lesc->sc_bres, off);
}
/**
* Read a 1, 2, or 4 byte data item from the PCI core's registers
* at @p offset.
*
* @param sc bhndb PCI driver state.
* @param offset register read offset.
* @param width item width (1, 2, or 4 bytes).
*/
static uint32_t
bhndb_pci_read_core(struct bhndb_pci_softc *sc, bus_size_t offset, u_int width)
{
struct resource *r;
bus_size_t r_offset;
int error;
error = bhndb_pci_get_core_regs(sc, offset, width, &r, &r_offset);
if (error) {
panic("no PCI register window mapping %#jx+%#x: %d",
(uintmax_t)offset, width, error);
}
switch (width) {
case 1:
return (bus_read_1(r, r_offset));
case 2:
return (bus_read_2(r, r_offset));
case 4:
return (bus_read_4(r, r_offset));
default:
panic("invalid width: %u", width);
}
}
int
smc_probe(device_t dev)
{
int rid, type, error;
uint16_t val;
struct smc_softc *sc;
struct resource *reg;
sc = device_get_softc(dev);
rid = 0;
type = SYS_RES_IOPORT;
error = 0;
if (sc->smc_usemem)
type = SYS_RES_MEMORY;
reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE);
if (reg == NULL) {
if (bootverbose)
device_printf(dev,
"could not allocate I/O resource for probe\n");
return (ENXIO);
}
/* Check for the identification value in the BSR. */
val = bus_read_2(reg, BSR);
if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
if (bootverbose)
device_printf(dev, "identification value not in BSR\n");
error = ENXIO;
goto done;
}
/*
* Try switching banks and make sure we still get the identification
* value.
*/
bus_write_2(reg, BSR, 0);
val = bus_read_2(reg, BSR);
if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
if (bootverbose)
device_printf(dev,
"identification value not in BSR after write\n");
error = ENXIO;
goto done;
}
#if 0
/* Check the BAR. */
bus_write_2(reg, BSR, 1);
val = bus_read_2(reg, BAR);
val = BAR_ADDRESS(val);
if (rman_get_start(reg) != val) {
if (bootverbose)
device_printf(dev, "BAR address %x does not match "
"I/O resource address %lx\n", val,
rman_get_start(reg));
error = ENXIO;
goto done;
}
#endif
/* Compare REV against known chip revisions. */
bus_write_2(reg, BSR, 3);
val = bus_read_2(reg, REV);
val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
if (smc_chip_ids[val] == NULL) {
if (bootverbose)
device_printf(dev, "Unknown chip revision: %d\n", val);
error = ENXIO;
goto done;
}
device_set_desc(dev, smc_chip_ids[val]);
done:
bus_release_resource(dev, type, rid, reg);
return (error);
}
static __inline uint16_t
smc_read_2(struct smc_softc *sc, bus_size_t offset)
{
return (bus_read_2(sc->smc_reg, offset));
}
static uint16_t
sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
{
struct sdhci_fdt_softc *sc = device_get_softc(dev);
return (bus_read_2(sc->mem_res[slot->num], off));
}
static struct resource *
cardbus_read_tuple_init(device_t cbdev, device_t child, uint32_t *start,
int *rid)
{
struct resource *res;
uint32_t space;
space = *start & PCIM_CIS_ASI_MASK;
switch (space) {
case PCIM_CIS_ASI_CONFIG:
DEVPRINTF((cbdev, "CIS in PCI config space\n"));
/* CIS in PCI config space need no initialization */
return (CIS_CONFIG_SPACE);
case PCIM_CIS_ASI_BAR0:
case PCIM_CIS_ASI_BAR1:
case PCIM_CIS_ASI_BAR2:
case PCIM_CIS_ASI_BAR3:
case PCIM_CIS_ASI_BAR4:
case PCIM_CIS_ASI_BAR5:
*rid = PCIR_BAR(space - PCIM_CIS_ASI_BAR0);
DEVPRINTF((cbdev, "CIS in BAR %#x\n", *rid));
break;
case PCIM_CIS_ASI_ROM:
*rid = PCIR_BIOS;
DEVPRINTF((cbdev, "CIS in option rom\n"));
break;
default:
device_printf(cbdev, "Unable to read CIS: Unknown space: %d\n",
space);
return (NULL);
}
/* allocate the memory space to read CIS */
res = bus_alloc_resource_any(child, SYS_RES_MEMORY, rid,
rman_make_alignment_flags(4096) | RF_ACTIVE);
if (res == NULL) {
device_printf(cbdev, "Unable to allocate resource "
"to read CIS.\n");
return (NULL);
}
DEVPRINTF((cbdev, "CIS Mapped to %#lx\n", rman_get_start(res)));
/* Flip to the right ROM image if CIS is in ROM */
if (space == PCIM_CIS_ASI_ROM) {
uint32_t imagesize;
uint32_t imagebase = 0;
uint32_t pcidata;
uint16_t romsig;
int romnum = 0;
int imagenum;
imagenum = (*start & PCIM_CIS_ROM_MASK) >> 28;
for (romnum = 0;; romnum++) {
romsig = bus_read_2(res,
imagebase + CARDBUS_EXROM_SIGNATURE);
if (romsig != 0xaa55) {
device_printf(cbdev, "Bad header in rom %d: "
"[%x] %04x\n", romnum, imagebase +
CARDBUS_EXROM_SIGNATURE, romsig);
cardbus_read_tuple_finish(cbdev, child, *rid,
res);
*rid = 0;
return (NULL);
}
/*
* If this was the Option ROM image that we were
* looking for, then we are done.
*/
if (romnum == imagenum)
break;
/* Find out where the next Option ROM image is */
pcidata = imagebase + bus_read_2(res,
imagebase + CARDBUS_EXROM_DATA_PTR);
imagesize = bus_read_2(res,
pcidata + CARDBUS_EXROM_DATA_IMAGE_LENGTH);
if (imagesize == 0) {
/*
* XXX some ROMs seem to have this as zero,
* can we assume this means 1 block?
*/
device_printf(cbdev, "Warning, size of Option "
"ROM image %d is 0 bytes, assuming 512 "
"bytes.\n", romnum);
imagesize = 1;
}
/* Image size is in 512 byte units */
imagesize <<= 9;
if ((bus_read_1(res, pcidata +
CARDBUS_EXROM_DATA_INDICATOR) & 0x80) != 0) {
device_printf(cbdev, "Cannot find CIS in "
"Option ROM\n");
cardbus_read_tuple_finish(cbdev, child, *rid,
res);
*rid = 0;
return (NULL);
}
imagebase += imagesize;
}
*start = imagebase + (*start & PCIM_CIS_ADDR_MASK);
} else {
static inline uint16_t
RD2(struct ffec_softc *sc, bus_size_t off)
{
return (bus_read_2(sc->mem_res, off));
}
/**
* ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
* @sc: I2C device context
* @off: the byte offset within the register bank to read from.
*
*
* LOCKING:
* No locking required
*
* RETURNS:
* 16-bit value read from the register.
*/
static inline uint16_t
ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
{
return (bus_read_2(sc->sc_mem_res, off));
}
