static int mt9m114_platform_init(struct i2c_client *client) { pmic_id = camera_pmic_probe(); if (pmic_id != PMIC_ROHM) return 0; v1p8_reg = regulator_get(&client->dev, "v1p8sx"); if (IS_ERR(v1p8_reg)) { dev_err(&client->dev, "v1p8s regulator_get failed\n"); return PTR_ERR(v1p8_reg); } v2p8_reg = regulator_get(&client->dev, "v2p85sx"); if (IS_ERR(v2p8_reg)) { regulator_put(v1p8_reg); dev_err(&client->dev, "v2p85sx regulator_get failed\n"); return PTR_ERR(v2p8_reg); } return 0; }
static int camera_pmic_set(bool flag) { int val; int ret = 0; if (pmic_id == PMIC_MAX) { pmic_id = camera_pmic_probe(); if (pmic_id == PMIC_MAX) return -EINVAL; } if (flag) { switch (pmic_id) { case PMIC_ROHM: ret = regulator_enable(v1p8_reg); if (ret) return ret; ret = regulator_enable(v2p8_reg); if (ret) regulator_disable(v1p8_reg); break; case PMIC_XPOWER: /* ALDO1 */ ret = intel_soc_pmic_writeb(ALDO1_SEL_REG, ALDO1_2P8V); if (ret) return ret; /* PMIC Output CTRL 3 for ALDO1 */ val = intel_soc_pmic_readb(ALDO1_CTRL3_REG); val |= (1 << ALDO1_CTRL3_SHIFT); ret = intel_soc_pmic_writeb(ALDO1_CTRL3_REG, val); if (ret) return ret; /* ELDO2 */ ret = intel_soc_pmic_writeb(ELDO2_SEL_REG, ELDO2_1P8V); if (ret) return ret; /* PMIC Output CTRL 2 for ELDO2 */ val = intel_soc_pmic_readb(ELDO2_CTRL2_REG); val |= (1 << ELDO2_CTRL2_SHIFT); ret = intel_soc_pmic_writeb(ELDO2_CTRL2_REG, val); break; case PMIC_TI: /* LDO9 */ ret = intel_soc_pmic_writeb(LDO9_REG, LDO9_2P8V_ON); if (ret) return ret; /* LDO10 */ ret = intel_soc_pmic_writeb(LDO10_REG, LDO10_1P8V_ON); if (ret) return ret; break; default: return -EINVAL; } } else { switch (pmic_id) { case PMIC_ROHM: ret = regulator_disable(v2p8_reg); ret += regulator_disable(v1p8_reg); break; case PMIC_XPOWER: val = intel_soc_pmic_readb(ALDO1_CTRL3_REG); val &= ~(1 << ALDO1_CTRL3_SHIFT); ret = intel_soc_pmic_writeb(ALDO1_CTRL3_REG, val); if (ret) return ret; val = intel_soc_pmic_readb(ELDO2_CTRL2_REG); val &= ~(1 << ELDO2_CTRL2_SHIFT); ret = intel_soc_pmic_writeb(ELDO2_CTRL2_REG, val); break; case PMIC_TI: /* LDO9 */ ret = intel_soc_pmic_writeb(LDO9_REG, LDO9_2P8V_OFF); if (ret) return ret; /* LDO10 */ ret = intel_soc_pmic_writeb(LDO10_REG, LDO10_1P8V_OFF); if (ret) return ret; break; default: return -EINVAL; } } return ret; }
static int camera_pmic_set(bool flag) { int val; int ret = 0; if (pmic_id == PMIC_MAX) { pmic_id = camera_pmic_probe(); if (pmic_id == PMIC_MAX) return -EINVAL; } if (flag) { switch (pmic_id) { case PMIC_ROHM: ret = regulator_enable(v2p8_reg); if (ret) return ret; ret = regulator_enable(v1p8_reg); if (ret) regulator_disable(v2p8_reg); break; case PMIC_XPOWER: /* ALDO1 */ ret = intel_mid_pmic_writeb(0x28, 0x16); if (ret) return ret; /* PMIC Output CTRL 3 for ALDO1 */ val = intel_mid_pmic_readb(0x13); val |= (1 << 5); ret = intel_mid_pmic_writeb(0x13, val); if (ret) return ret; /* ELDO2 */ ret = intel_mid_pmic_writeb(0x1A, 0x16); if (ret) return ret; /* PMIC Output CTRL 2 for ELDO2 */ val = intel_mid_pmic_readb(0x12); val |= (1 << 1); ret = intel_mid_pmic_writeb(0x12, val); break; case PMIC_TI: /* LDO9 */ ret = intel_mid_pmic_writeb(0x49, 0x2F); if (ret) return ret; /* LDO10 */ ret = intel_mid_pmic_writeb(0x4A, 0x59); if (ret) return ret; /* LDO11 */ ret = intel_mid_pmic_writeb(0x4B, 0x59); if (ret) return ret; break; default: return -EINVAL; } } else { switch (pmic_id) { case PMIC_ROHM: ret = regulator_disable(v2p8_reg); ret += regulator_disable(v1p8_reg); break; case PMIC_XPOWER: val = intel_mid_pmic_readb(0x13); val &= ~(1 << 5); ret = intel_mid_pmic_writeb(0x13, val); if (ret) return ret; val = intel_mid_pmic_readb(0x12); val &= ~(1 << 1); ret = intel_mid_pmic_writeb(0x12, val); break; case PMIC_TI: /* LDO9 */ ret = intel_mid_pmic_writeb(0x49, 0x2E); if (ret) return ret; /* LDO10 */ ret = intel_mid_pmic_writeb(0x4A, 0x58); if (ret) return ret; /* LDO11 */ ret = intel_mid_pmic_writeb(0x4B, 0x58); if (ret) return ret; break; default: return -EINVAL; } } return ret; }