/*******************************************************************************
* @fn cc2500_disable_addressing( );
* @brief Disable address checking
* ****************************************************************************/
void cc2500_disable_addressing()
{
uint8_t tmp_reg;
tmp_reg = ( cc_read_reg( TI_CCxxx0_PKTCTRL1 ) & ~0x03 );
cc_write_reg( TI_CCxxx0_PKTCTRL1, tmp_reg );
}
/*******************************************************************************
* @fn uint8_t receive_packet( uint8_t* p_buffer, uint8_t* length )
* @brief Receive packet from the radio using CC2500
* ****************************************************************************/
uint8_t receive_packet( uint8_t* p_buffer, uint8_t* length )
{
uint8_t status[2];
uint8_t packet_length;
volatile uint8_t Testo = 0;
volatile uint8_t ReadStatusValue =0;
ReadStatusValue = cc_read_status( TI_CCxxx0_RXBYTES );
// Make sure there are bytes to be read in the FIFO buffer
if ( (ReadStatusValue & TI_CCxxx0_NUM_RXBYTES ) )
{
// Read the first byte which contains the packet length
packet_length = cc_read_reg( TI_CCxxx0_RXFIFO );
// Make sure the packet length is smaller than our buffer
if ( packet_length <= *length )
{
// Read the rest of the packet
cc_read_burst_reg( TI_CCxxx0_RXFIFO, p_buffer, packet_length );
// Return packet size in length variable
*length = packet_length;
// Read two byte status
cc_read_burst_reg( TI_CCxxx0_RXFIFO, status, 2 );
// Append status bytes to buffer
memcpy( &p_buffer[packet_length], status, 2 );
// Return 1 when CRC matches, 0 otherwise
return ( status[TI_CCxxx0_LQI_RX] & TI_CCxxx0_CRC_OK );
}
else
{
// If the packet is larger than the buffer, flush the RX FIFO
*length = packet_length;
// Flush RX FIFO
cc_strobe(TI_CCxxx0_SFRX); // Flush RXFIFO
return 0;
}
}
return 0;
}
uint8_t writeRFSettings(void)
{
uint8_t temp = 0;
uint8_t returnValue = 0;
// FIXME Add uscib0 files
// Write register settings
do{
cc_write_reg(TI_CCxxx0_IOCFG2, GDO2_PIN_SETTING); // GDO2 output pin config.
temp = cc_read_reg(TI_CCxxx0_IOCFG2);
if(temp != GDO2_PIN_SETTING)
{
while(1)
{
temp = cc_read_reg(TI_CCxxx0_IOCFG2);
}
returnValue = 1;
break;
}
cc_write_reg(TI_CCxxx0_IOCFG0, GDO0_PIN_SETTING); // GDO0 output pin config.
temp = cc_read_reg(TI_CCxxx0_IOCFG0);
//cc_write_reg(TI_CCxxx0_IOCFG0, 0x01); // GDO0 output pin config.
//cc_write_reg(TI_CCxxx0_PKTLEN, 0x3D); // Packet length.
cc_write_reg(TI_CCxxx0_PKTLEN, 0x7); // Packet length.
//cc_write_reg(TI_CCxxx0_PKTCTRL1, 0x4); // Packet automation control. // Was 0xE
cc_write_reg(TI_CCxxx0_PKTCTRL1, CRC_AUTO_FLUSH); // Packet automation control. // Was 0xE
temp = cc_read_reg(TI_CCxxx0_PKTCTRL1);
//cc_write_reg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
cc_write_reg(TI_CCxxx0_PKTCTRL0, CRC_EN); // Packet automation control.
temp = cc_read_reg(TI_CCxxx0_PKTCTRL0);
cc_write_reg(TI_CCxxx0_ADDR, 0x00); // Device address.
cc_write_reg(TI_CCxxx0_CHANNR, 0x00); // Channel number.
cc_write_reg(TI_CCxxx0_FSCTRL1, 0x07); // Freq synthesizer control.
temp = cc_read_reg(TI_CCxxx0_FSCTRL1);
if(temp != 0x7)
{
while(1);
returnValue = 1;
break;
}
cc_write_reg(TI_CCxxx0_FSCTRL0, 0x00); // Freq synthesizer control.
cc_write_reg(TI_CCxxx0_FREQ2, 0x5D); // Freq control word, high byte
cc_write_reg(TI_CCxxx0_FREQ1, 0x93); // Freq control word, mid byte.
cc_write_reg(TI_CCxxx0_FREQ0, 0xB1); // Freq control word, low byte.
cc_write_reg(TI_CCxxx0_MDMCFG4, 0x2D); // Modem configuration. ////WAS 2D, determines data rate !!!!!!!!!!!!!!!!!!!!!!
cc_write_reg(TI_CCxxx0_MDMCFG3, 0x3B); // Modem configuration.
cc_write_reg(TI_CCxxx0_MDMCFG2, 0x73); // Modem configuration. // MSK(0x7), 32 bytes of SYNC (0x3) :0x73
cc_write_reg(TI_CCxxx0_MDMCFG1, 0x22); // Modem configuration. //
cc_write_reg(TI_CCxxx0_MDMCFG0, 0xF8); // Modem configuration.
cc_write_reg(TI_CCxxx0_DEVIATN, 0x00); // Modem dev (when FSK mod en)
cc_write_reg(TI_CCxxx0_MCSM1 , 0x2F); //MainRadio Cntrl State Machine
cc_write_reg(TI_CCxxx0_MCSM0 , 0x18); //MainRadio Cntrl State Machine
cc_write_reg(TI_CCxxx0_FOCCFG, 0x1D); // Freq Offset Compens. Config
cc_write_reg(TI_CCxxx0_BSCFG, 0x1C); // Bit synchronization config.
cc_write_reg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
cc_write_reg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
cc_write_reg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
cc_write_reg(TI_CCxxx0_FREND1, 0xB6); // Front end RX configuration.
cc_write_reg(TI_CCxxx0_FREND0, 0x10); // Front end RX configuration.
cc_write_reg(TI_CCxxx0_FSCAL3, 0xEA); // Frequency synthesizer cal.
cc_write_reg(TI_CCxxx0_FSCAL2, 0x0A); // Frequency synthesizer cal.
cc_write_reg(TI_CCxxx0_FSCAL1, 0x00); // Frequency synthesizer cal.
cc_write_reg(TI_CCxxx0_FSCAL0, 0x11); // Frequency synthesizer cal. /// changes with buad rate!!!!!!!!!!!!!!!!!!!!!!!!!!
cc_write_reg(TI_CCxxx0_FSTEST, 0x59); // Frequency synthesizer cal.
cc_write_reg(TI_CCxxx0_TEST2, 0x88); // Various test settings.
cc_write_reg(TI_CCxxx0_TEST1, 0x31); // Various test settings.
cc_write_reg(TI_CCxxx0_TEST0, 0x0B); // Various test settings.
}while(0);
return returnValue;
}
