/**
* Initalizes both (Rx/Tx) DMA fifo's and related management structures
*/
static int ccat_eth_priv_init_dma(struct ccat_eth_priv *priv)
{
struct ccat_dma_mem *const dma = &priv->dma_mem;
struct pci_dev *const pdev = priv->func->ccat->pdev;
void __iomem *const bar_2 = priv->func->ccat->bar_2;
const u8 rx_chan = priv->func->info.rx_dma_chan;
const u8 tx_chan = priv->func->info.tx_dma_chan;
int status = 0;
dma->dev = &pdev->dev;
dma->size = CCAT_ALIGNMENT * 3;
dma->base =
dma_zalloc_coherent(dma->dev, dma->size, &dma->phys, GFP_KERNEL);
if (!dma->base || !dma->phys) {
pr_err("init DMA memory failed.\n");
return -ENOMEM;
}
priv->rx_fifo.ops = &dma_rx_fifo_ops;
status = ccat_dma_init(dma, rx_chan, bar_2, &priv->rx_fifo);
if (status) {
pr_info("init RX DMA memory failed.\n");
ccat_dma_free(priv);
return status;
}
priv->tx_fifo.ops = &dma_tx_fifo_ops;
status = ccat_dma_init(dma, tx_chan, bar_2, &priv->tx_fifo);
if (status) {
pr_info("init TX DMA memory failed.\n");
ccat_dma_free(priv);
return status;
}
return ccat_hw_disable_mac_filter(priv);
}
static int ccat_eth_dma_fifo_init(struct ccat_eth_dma_fifo *fifo,
void __iomem * const fifo_reg,
fifo_add_function add, size_t channel,
struct ccat_eth_priv *const priv)
{
if (0 !=
ccat_dma_init(&fifo->dma, channel, priv->ccatdev->bar[2].ioaddr,
&priv->ccatdev->pdev->dev)) {
pr_info("init DMA%llu memory failed.\n", (u64) channel);
return -1;
}
fifo->add = add;
fifo->end = ((struct ccat_eth_frame *)fifo->dma.virt) + FIFO_LENGTH;
fifo->reg = fifo_reg;
return 0;
}
