kal_bool ccci_lb_it_init(){
#if defined(__MTK_TARGET__) //MODIS doesn't need CCCI IT loopback
kal_uint32 idx;
CCCI_RETURNVAL_T ccci_ret;
ccci_printf(CCCI_TRACE, CCCI_MOD_IT, "===> ccci_it_init\n");
for(idx = 0; idx < CCCI_LB_IT_PORT_NUM; idx++){
ccci_printf(CCCI_TRACE, CCCI_MOD_IT, "===> ccci_it_init initialize ccci_duser_it_port[%d]\n", idx);
ccci_ret = ccci_init(ccci_lb_it_port[idx].ch_dl,ccci_lb_it_buff_tx_cb);
if(CCCI_IN_USE == ccci_ret){
/* channel has been registered in normal process, deinit and reinit */
ccci_deinit(ccci_lb_it_port[idx].ch_dl);
ccci_ret = ccci_init(ccci_lb_it_port[idx].ch_dl,ccci_lb_it_buff_tx_cb);
}
ASSERT(CCCI_SUCCESS == ccci_ret);
ccci_ret = ccci_init(ccci_lb_it_port[idx].ch_ul,ccci_lb_it_buff_rx_lb);
if(CCCI_IN_USE == ccci_ret){
/* channel has been registered in normal process, deinit and reinit */
ccci_deinit(ccci_lb_it_port[idx].ch_ul);
ccci_ret = ccci_init(ccci_lb_it_port[idx].ch_ul,ccci_lb_it_buff_rx_lb);
}
ASSERT(CCCI_SUCCESS == ccci_ret);
}
#endif
return KAL_TRUE;
}
void dcl_pmic6327_init(void){
kal_uint32 i;
#if defined(__MODEM_CCCI_EXIST__) && !defined(__UBL__) && !defined(__FUE__)
ccci_init(CCCI_PMIC_CHANNEL, NULL);
ccci_init(CCCI_PMIC_ACK_CHANNEL, pmic6327_ccci_callback);
#endif
i2c_pmic_init();
pmu_control_handler = PMIC6327_control_handler;
pmu_parameter_size = GETARRNUM(pmu_parameter_table);
#if !defined(__UBL__) && !defined(__FUE__)
i2cDcmHandle=DCM_GetHandle();
#endif
//Disable deglitch.
dcl_pmic6327_byte_write(0x01, 0x00, PMIC_BANK0);
//Speed up I2C
i2c_pmic_set_speed(0, 5);
pmic6327_eco_version = PMIC6327_ECO_1_VERSION;
// Get PMIC6327 ECO version
{
kal_uint16 eco_version = 0;
eco_version = dcl_pmic6327_byte_return(VERSION_ADDR, PMIC_BANK0);
if (eco_version == PMIC6327_E1_VERSION)
{
pmic6327_eco_version = PMIC6327_ECO_1_VERSION;
}
else// if(eco_version == PMIC6327_E2_CID_CODE)
{
pmic6327_eco_version = PMIC6327_ECO_2_VERSION;
}
}
for (i = 0;i < PMIC_BANK0_REG_NUM;i++){
pmic6327_reg[PMIC_BANK0][i] = dcl_pmic6327_byte_return(i, PMIC_BANK0);
}
dcl_pmic6327_internal_init();
#if (defined(MT6280_S00))
//Set VCore sleep voltage to 1.1V for MT6280 E1
dcl_pmic6327_byte_write(0x56, 0x10, 0);
#elif (defined(MT6280_S01))
//Set VCore normal voltage to 1.1V for MT6280 E2
dcl_pmic6327_byte_write(0x55, 0x10, 0);
#endif
pmic6327_customization_init();
#if !defined(__UBL__) && !defined(__FUE__)
pmu_drv_tool_customization_init();
#endif //#if !defined(__UBL__) && !defined(__FUE__)
}
void pmic6326_ccci_init(void)
{
#ifndef BY_PASS_PMIC_CCCI_DRIVER
kal_uint32 addr;
kal_uint32 size = 0;
// 1. Get share memory info
addr = ccci_query_sharemem_addr(CCCI_PMIC_CHANNEL, &size);
// Make sure share memory size is larger than the share memory info structure
ASSERT(size >= sizeof(pmic6326_share_mem_info));
pPMIC6326ShareMemInfo = (pmic6326_share_mem_info *)addr;
//ccci_init(CCCI_PMIC_CHANNEL, pmic6326_ccci_callback);
ccci_init(CCCI_PMIC_ACK_CHANNEL, pmic6326_ccci_callback);
#if defined(DEBUG_PMIC_CCCI_UT)
pmic6326_ccci_ut_main();
#endif // #if defined(DEBUG_PMIC_CCCI_UT)
#endif // #ifndef BY_PASS_PMIC_CCCI_DRIVER
}
/*************************************************************************
* FUNCTION
* void ccci_exception_handshake
*
* DESCRIPTION
* This function .
*
* PARAMETERS
* channel - logical channel
* *
* RETURNS
* The address of the share memory of the input logical channel
*
*************************************************************************/
void ccci_exception_handshake(void){
#if defined(__MODEM_CCCI_EXIST__)&& !defined(__MODEM_CARD__)
CCCI_BUFF_T *buff;
kal_uint32 p_cache_aligned;
kal_uint32 gpd_num;
qbm_gpd *p_first_gpd, *p_last_gpd;
//kal_uint32 rcv_size = 0;
// ensure in the exception state
if(INT_QueryExceptionStatus() == KAL_FALSE)
return;
//we block here for debuging
//if(ccci_exception_state != CCCI_EXPT_CLEAR_CH_ST) while(1);
//- Avoid to use kal_mem_cpy
//- HW bug
ccci_init(CCCI_CONTROL_CHANNEL, ccci_except_ack);
ccci_init(CCCI_CONTROL_CHANNEL_ACK, ccci_except_ack);
// exception only have single thread, need to do polling mode
/* initialize polling mode GPD */
ASSERT(CCCI_EXCEPT_POLLING_MODE_BUF_SZ >= 2*CPU_CACHE_LINE_SIZE);
/*make p_gpd aligned to CPU_CACHE_LINE_SIZE_MASK*/
p_cache_aligned = (kal_uint32)g_ccci_expect_polling_buf_tx;
if(p_cache_aligned&CPU_CACHE_LINE_SIZE_MASK) {
p_cache_aligned = ((kal_uint32)(g_ccci_expect_polling_buf_tx)&~CPU_CACHE_LINE_SIZE_MASK);
p_cache_aligned += CPU_CACHE_LINE_SIZE;
}
// The reason + QBM_HEAD_SIZE is for ROME E1, cldma needs to record this buff whether is cacheable or non-cacheable
ccci_except_polling_gpd_tx = (qbm_gpd *)(p_cache_aligned + QBM_HEAD_SIZE);
CCCIDEV_RST_CCCI_COMM_GPD_LIST(ccci_except_polling_gpd_tx, ccci_except_polling_gpd_tx);
//format Rx GPD
p_cache_aligned = (kal_uint32)g_ccci_expect_polling_buf_rx;
if(p_cache_aligned&CPU_CACHE_LINE_SIZE_MASK) {
p_cache_aligned = ((kal_uint32)(g_ccci_expect_polling_buf_rx)&~CPU_CACHE_LINE_SIZE_MASK);
p_cache_aligned += CPU_CACHE_LINE_SIZE;
}
// The reason + QBM_HEAD_SIZE is for ROME E1, cldma needs to record this buff whether is cacheable or non-cacheable
ccci_except_polling_gpd_rx = (qbm_gpd *)(p_cache_aligned + QBM_HEAD_SIZE);
CCCIDEV_RST_CCCI_COMM_GPD_LIST(ccci_except_polling_gpd_rx, ccci_except_polling_gpd_rx);
//format Rx 2nd GPD
p_cache_aligned = (kal_uint32)g_ccci_expect_polling_buf_rx2;
if(p_cache_aligned&CPU_CACHE_LINE_SIZE_MASK) {
p_cache_aligned = ((kal_uint32)(g_ccci_expect_polling_buf_rx2)&~CPU_CACHE_LINE_SIZE_MASK);
p_cache_aligned += CPU_CACHE_LINE_SIZE;
}
// The reason + QBM_HEAD_SIZE is for ROME E1, cldma needs to record this buff whether is cacheable or non-cacheable
ccci_except_polling_gpd_rx2 = (qbm_gpd *)(p_cache_aligned + QBM_HEAD_SIZE);
CCCIDEV_RST_CCCI_COMM_GPD_LIST(ccci_except_polling_gpd_rx2, ccci_except_polling_gpd_rx2);
//step 0. config rx gpd next pointer
QBM_DES_SET_NEXT(ccci_except_polling_gpd_rx, ccci_except_polling_gpd_rx2);
//step 1. send TX handshake pkt
buff = CCCIDEV_GET_QBM_DATAPTR(ccci_except_polling_gpd_tx);
buff->data[0] = MD_EX_MAGIC;
buff->data[1] = CCMSG_ID_EXCEPTION_CHECK;
buff->channel = CCCI_CONTROL_CHANNEL;
buff->reserved = MD_EX_CHK_ID;
ccci_debug_add_seq(buff, CCCI_DEBUG_ASSERT_BIT); // add ccci seq
QBM_DES_SET_DATALEN(ccci_except_polling_gpd_tx, sizeof(CCCI_BUFF_T));
QBM_DES_SET_DATALEN(ccci_except_polling_gpd_tx->p_data_tbd, sizeof(CCCI_BUFF_T));
qbm_cal_set_checksum((kal_uint8 *)ccci_except_polling_gpd_tx);
qbm_cal_set_checksum((kal_uint8 *)ccci_except_polling_gpd_tx->p_data_tbd);
QBM_CACHE_FLUSH(ccci_except_polling_gpd_tx, sizeof(qbm_gpd));
QBM_CACHE_FLUSH(ccci_except_polling_gpd_tx->p_data_tbd, sizeof(qbm_gpd));
QBM_CACHE_FLUSH(buff, sizeof(CCCI_BUFF_T));
ex_set_step_logging(EX_AUTO_STEP); //0x41
//step 2. polling echoed rx handshake pkt (need two GPD, one for tail)
// TODO:Need to revise the API, shall use exception API (after channle reset flow is done)
#ifdef SWITCH_TO_EXCEPTION_IO
p_first_gpd = p_last_gpd = ccci_except_polling_gpd_tx;
ccci_except_set_gpd(CCCI_CONTROL_CHANNEL, p_first_gpd, p_last_gpd);
gpd_num = 0;
do{
ccci_except_hif_st(CCCI_CONTROL_CHANNEL);
ccci_except_poll_gpd(CCCI_CONTROL_CHANNEL, (void **)&p_first_gpd, (void **)&p_last_gpd, &gpd_num);
}while(0 == gpd_num);
CCCIDEV_RST_CCCI_COMM_GPD_LIST(p_first_gpd, p_last_gpd);
ex_set_step_logging(EX_AUTO_STEP); //0x42
p_first_gpd = ccci_except_polling_gpd_rx;
p_last_gpd = ccci_except_polling_gpd_rx2;
do{
ccci_except_set_gpd(CCCI_CONTROL_CHANNEL_ACK, p_first_gpd, p_last_gpd);
gpd_num = 0;
do{
ccci_except_hif_st(CCCI_CONTROL_CHANNEL_ACK);
ccci_except_poll_gpd(CCCI_CONTROL_CHANNEL_ACK, (void **)&p_first_gpd, (void **)&p_last_gpd, &gpd_num);
}while(0 == gpd_num);
buff = CCCIDEV_GET_QBM_DATAPTR(ccci_except_polling_gpd_rx);
//rcv_size = CCCIDEV_GET_QBM_DATALEN(ccci_except_polling_gpd_rx); // FIXME
QBM_CACHE_INVALID(buff, sizeof(CCCI_BUFF_T));
ccci_debug_check_seq(buff); // check ccci seq
if (buff->reserved == MD_EX_CHK_ID){
ex_set_step_logging(EX_AUTO_STEP); //0x43
ccci_exception_handshake_done = KAL_TRUE;
CCCIDEV_RST_CCCI_COMM_GPD_LIST(p_first_gpd, p_last_gpd);
ccci_except_set_gpd(CCCI_CONTROL_CHANNEL_ACK, p_first_gpd, p_last_gpd); //reload to CCCI_CONTROL_CHANNEL_ACK
break;
}
else
{
//dump date
ex_fire_extern_step_logging(0xFFFFFFFF);
ex_fire_extern_step_logging(buff->data[0]);
ex_fire_extern_step_logging(buff->data[1]);
ex_fire_extern_step_logging(buff->channel);
ex_fire_extern_step_logging(buff->reserved);
ex_fire_extern_step_logging(0xFFFFFFFF);
}
CCCIDEV_RST_CCCI_COMM_GPD_LIST(p_first_gpd, p_last_gpd);
}while(1);
#else
ccci_exception_check_write_result = ccci_polling_io(CCCI_CONTROL_CHANNEL, ccci_except_polling_gpd_tx, KAL_TRUE);
CCCIDEV_RST_CCCI_COMM_GPD_LIST(ccci_except_polling_gpd_tx, ccci_except_polling_gpd_tx);
while(CCCI_SUCCESS == (ccci_exception_handshake_done = ccci_polling_io(CCCI_CONTROL_CHANNEL_ACK, ccci_except_polling_gpd_tx, KAL_FALSE))){
buff = CCCIDEV_GET_QBM_DATAPTR(ccci_except_polling_gpd_tx);
QBM_CACHE_INVALID(buff, sizeof(CCCI_BUFF_T));
ccci_debug_check_seq(buff); // check ccci seq
if (buff->reserved == MD_EX_CHK_ID){
CCCIDEV_RST_CCCI_COMM_GPD_LIST(ccci_except_polling_gpd_tx, ccci_except_polling_gpd_tx);
break;
}
CCCIDEV_RST_CCCI_COMM_GPD_LIST(ccci_except_polling_gpd_tx, ccci_except_polling_gpd_tx);
}
#endif
ex_set_step_logging(EX_AUTO_STEP); //0x44
ccci_exception_state = CCCI_EXPT_HANDSHAKE_ST;
#ifdef CCCI_EXCETION_PRE_TEST
ccci_exception_info_passed_pre();
#endif
#endif
}
void Drv_Init_Phase1(void)
{
#if defined(DRV_GPT_GPT3)
DCL_HANDLE gpt_handle;
#endif //defined(DRV_GPT_GPT3)
#ifndef DRV_RTC_NOT_EXIST
DCL_HANDLE rtc_handler;
#endif //#ifndef DRV_RTC_NOT_EXIST
DCL_HANDLE uart_handle;
UART_CTRL_INIT_T data_init;
extern Seriport_HANDLER_T Uart_Drv_Handler;
#ifdef __USB_COM_PORT_ENABLE__
DCL_HANDLE usb_dcl_handle;
DCL_BOOL dcl_data;
kal_bool b_is_dl_mode;
usb_dcl_handle = DclUSB_DRV_Open(DCL_USB, FLAGS_NONE);
DclUSB_DRV_Control(usb_dcl_handle, USB_DRV_CMD_USBDL_UPDATE_USB_DL_MODE, NULL);
DclUSB_DRV_Control(usb_dcl_handle, USB_DRV_CMD_USBDL_IS_USB_DL_MODE, (DCL_CTRL_DATA_T *)&dcl_data);
b_is_dl_mode = (kal_bool)dcl_data;
if(b_is_dl_mode == KAL_TRUE)
{
UPLL_Enable(UPLL_OWNER_USB);
}
DclUSB_DRV_Close(usb_dcl_handle);
#endif //__USB_COM_PORT_ENABLE__
#if defined(__HW_US_TIMER_SUPPORT__ )
USC_Start();
#endif
#ifdef __BACKUP_DOWNLOAD_RESTORE_WITHOUT_BATTERY__
if (INT_GetSysStaByCmd(CHK_USB_META_WO_BAT, NULL)==KAL_TRUE)
{
DCL_HANDLE handle;
DclPMU_Initialize();
handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
DclPMU_Control(handle, CHR_SET_CHARGE_WITHOUT_BATTERY, NULL);
DclPMU_Close(handle);
}
#endif //#ifdef __BACKUP_DOWNLOAD_RESTORE_WITHOUT_BATTERY__
print_bootup_trace_enter(SST_INIT_DRV1_DRVHISR);
drv_hisr_init();
print_bootup_trace_exit(SST_INIT_DRV1_DRVHISR);
#if defined(__DSP_FCORE4__)
print_bootup_trace_enter(SST_INIT_DRV1_MDCIHW);
mdci_hw_init(1,0x0);
print_bootup_trace_exit(SST_INIT_DRV1_MDCIHW);
#endif
#if defined(__SMART_PHONE_MODEM__)
print_bootup_trace_enter(SST_INIT_DRV1_CCCI);
ccif_init(1,0x0);
ipc_msgsvc_init();
FS_CCCI_Init();
ccci_init(CCCI_FS_CHANNEL, FS_CCCI_Callback);
ccci_init(CCCI_FS_ACK_CHANNEL, FS_CCCI_Callback);
uart_handle = DclSerialPort_Open(uart_port_tst_ccci, 0);
DclSerialPort_RegisterCallback(uart_handle, &CCCI_Uart_Drv_Handler);
uart_handle = DclSerialPort_Open(uart_port_at_ccci, 0);
DclSerialPort_RegisterCallback(uart_handle, &CCCI_Uart_Drv_Handler);
#if defined(__UPS_SUPPORT__)
uart_handle = DclSerialPort_Open(uart_port_ccmni1_ccci, 0);
DclSerialPort_RegisterCallback(uart_handle, &CCCI_Uart_Drv_Handler);
uart_handle = DclSerialPort_Open(uart_port_ccmni2_ccci, 0);
DclSerialPort_RegisterCallback(uart_handle, &CCCI_Uart_Drv_Handler);
uart_handle = DclSerialPort_Open(uart_port_ccmni3_ccci, 0);
DclSerialPort_RegisterCallback(uart_handle, &CCCI_Uart_Drv_Handler);
#endif /* __UPS_SUPPORT__ */
uart_handle = DclSerialPort_Open(uart_port_gps_ccci, 0);
DclSerialPort_RegisterCallback(uart_handle, &CCCI_Uart_Drv_Handler);
print_bootup_trace_exit(SST_INIT_DRV1_CCCI);
#endif /* __SMART_PHONE_MODEM__ */
#if defined(DRV_EMIMPU)
print_bootup_trace_enter(SST_INIT_DRV1_EMIMPU);
emimpu_init();
print_bootup_trace_exit(SST_INIT_DRV1_EMIMPU);
#endif /* DRV_EMIMPU */
print_bootup_trace_enter(SST_INIT_DRV1_LPWR);
lpwr_init();
print_bootup_trace_exit(SST_INIT_DRV1_LPWR);
print_bootup_trace_enter(SST_INIT_DRV1_DRVPDN);
DRVPDN_ini();
print_bootup_trace_exit(SST_INIT_DRV1_DRVPDN);
print_bootup_trace_enter(SST_INIT_DRV1_PWM);
DclPWM_Initialize();
print_bootup_trace_exit(SST_INIT_DRV1_PWM);
/*To get all customized data*/
print_bootup_trace_enter(SST_INIT_DRV1_CUSTOM);
DclSADC_Initialize();
Drv_Customize_Init();
custom_drv_init();
print_bootup_trace_exit(SST_INIT_DRV1_CUSTOM);
#if defined(DRV_GPT_GPT3)
print_bootup_trace_enter(SST_INIT_DRV1_GPT3);
/*turn on gpt3 to count powen on period*/
DclFGPT_Initialize();
gpt_handle=DclFGPT_Open(DCL_GPT_FreeRUN3,0);
DclFGPT_Control(gpt_handle,FGPT_CMD_START,0);
DclFGPT_Close(gpt_handle);
print_bootup_trace_exit(SST_INIT_DRV1_GPT3);
#endif
#if !defined(__L1_STANDALONE__) && !defined(__MAUI_BASIC__) && !defined(__SMART_PHONE_MODEM__)
print_bootup_trace_enter(SST_INIT_DRV1_VISUAL);
Visual_Init();
print_bootup_trace_exit(SST_INIT_DRV1_VISUAL);
#endif /*!defined(__L1_STANDALONE__) && !defined(__MAUI_BASIC__) && !defined(__SMART_PHONE_MODEM__)*/
#if defined(DRV_TIMING_DEBUG) && defined(DRV_GPT_6218B_GPT3_TIMING_DEBUG)
DRV_MISC_WriteReg(0x8010001c,1);
DRV_MISC_WriteReg(0x80100024,0x04);
//DRV_WriteReg(0x80100024,1); // (1/16K)
#endif
#ifdef DRV_MISC_DMA_NO_MEMCPY
DRV_MEMCPY = (MEMCPY_FUNC)0x48000150;
#elif defined(DRV_MISC_DMA_MEMCPY)
DRV_MEMCPY_PTR = (MEMCPY_FUNC)0x48000134;
#endif
print_bootup_trace_enter(SST_INIT_DRV1_GPTI);
DclSGPT_Initialize();
print_bootup_trace_exit(SST_INIT_DRV1_GPTI);
print_bootup_trace_enter(SST_INIT_DRV1_WDT);
WDT_init();
print_bootup_trace_exit(SST_INIT_DRV1_WDT);
print_bootup_trace_enter(SST_INIT_DRV1_DMA);
DMA_Ini();
print_bootup_trace_exit(SST_INIT_DRV1_DMA);
#ifndef DRV_RTC_NOT_EXIST
// need to set XOSC earlier
print_bootup_trace_enter(SST_INIT_DRV1_XOSC);
rtc_handler = DclRTC_Open(DCL_RTC,FLAGS_NONE);
DclRTC_Control(rtc_handler, RTC_CMD_SETXOSC, (DCL_CTRL_DATA_T *)NULL);
print_bootup_trace_exit(SST_INIT_DRV1_XOSC);
#endif /*DRV_RTC_NOT_EXIST*/
print_bootup_trace_enter(SST_INIT_DRV1_ADC);
DclHADC_Initialize( );
print_bootup_trace_exit(SST_INIT_DRV1_ADC);
#ifdef __CS_FAC_DET__
print_bootup_trace_enter(SST_INIT_DRV1_CSFACDET);
cs_fac_det = cs_fac_det_get_interface();
cs_fac_det->drv_init();
print_bootup_trace_exit(SST_INIT_DRV1_CSFACDET);
#endif // #ifdef __CS_FAC_DET__
#ifdef __DRV_EXT_ACCESSORY_DETECTION__
#ifdef __USB_COM_PORT_ENABLE__
usb_dcl_handle = DclUSB_DRV_Open(DCL_USB, FLAGS_NONE);
DclUSB_DRV_Control(usb_dcl_handle, USB_DRV_CMD_USBDL_IS_USB_DL_MODE, (DCL_CTRL_DATA_T *)&dcl_data);
b_is_dl_mode = (kal_bool)dcl_data;
DclUSB_DRV_Close(usb_dcl_handle);
if(b_is_dl_mode == KAL_FALSE)
#endif
{
print_bootup_trace_enter(SST_INIT_DRV1_EXTACCDET);
aux_ext_acc_det = aux_custom_get_ext_accessory_det();
aux_ext_acc_det->drv_init();
print_bootup_trace_exit(SST_INIT_DRV1_EXTACCDET);
}
#endif // #ifdef __DRV_EXT_ACCESSORY_DETECTION__
//#if (defined(__ACCDET_SUPPORT__) && !defined(__L1_STANDALONE__))
print_bootup_trace_enter(SST_INIT_DRV1_ACCDET);
DclAUX_Initialize();
print_bootup_trace_exit(SST_INIT_DRV1_ACCDET);
//#endif //#if defined(__ACCDET_SUPPORT__)
#if defined(__RESOURCE_MANAGER__)
print_bootup_trace_enter(SST_INIT_DRV1_RM);
RMInit();
print_bootup_trace_exit(SST_INIT_DRV1_RM);
#endif //__RESOURCE_MANAGER__
#ifndef DRV_LCD_NOT_EXIST
print_bootup_trace_enter(SST_INIT_DRV1_LCD);
lcd_system_init();
print_bootup_trace_exit(SST_INIT_DRV1_LCD);
#endif /*DRV_LCD_NOT_EXIST*/
#ifndef DRV_RTC_NOT_EXIST
#ifdef DRV_RTC_HW_CALI
print_bootup_trace_enter(SST_INIT_DRV1_RTCHW);
DclRTC_Control(rtc_handler, RTC_CMD_HW_INIT, (DCL_CTRL_DATA_T *)NULL);
print_bootup_trace_exit(SST_INIT_DRV1_RTCHW);
#endif
#endif /*DRV_RTC_NOT_EXIST*/
DclPW_Initialize();
DclPMU_Initialize();
Drv_PW_Init();
/* update the system boot mode */
/*lint -e552*/
system_boot_mode = Drv_query_boot_mode();
/*lint +e552*/
print_boot_mode();
#ifdef __DMA_UART_VIRTUAL_FIFO__
// print_bootup_trace_enter(SST_INIT_DRV1_DMAVFIFO);
// DMA_Vfifo_init();
// print_bootup_trace_exit(SST_INIT_DRV1_DMAVFIFO);
#if defined(__MD_STANDALONE__)
// This is to configure AP side VFIFO ALT register, to avoid un-init AP side DMA setting
// conflict MD side setting
// This is only used in MD DVT load, when both side are ready, we shouldn't overwrite AP side setting via back door
// Hack DMA channel 13 (VFIFO channel) in AP side in order to avoid conflict
*(volatile kal_uint32 *)(0xF0022000 + 0xD40) = 0x3F;
// Hack DMA channel 14 (VFIFO channel) in AP side in order to avoid conflict
*(volatile kal_uint32 *)(0xF0022000 + 0xE40) = 0x3F;
#endif // #if defined(__MD_STANDALONE__)
#endif
print_bootup_trace_enter(SST_INIT_DRV1_UART1);
data_init.u4Flag = KAL_FALSE;
uart_handle = DclSerialPort_Open(uart_port1, 0);
DclSerialPort_RegisterCallback(uart_handle, &Uart_Drv_Handler);
// Initialization
DclSerialPort_Control(uart_handle,SIO_CMD_INIT,(DCL_CTRL_DATA_T *)&data_init);
print_bootup_trace_exit(SST_INIT_DRV1_UART1);
// Register the callback function
print_bootup_trace_enter(SST_INIT_DRV1_UART2);
uart_handle = DclSerialPort_Open(uart_port2, 0);
DclSerialPort_RegisterCallback(uart_handle, &Uart_Drv_Handler);
// Initialization
DclSerialPort_Control(uart_handle,SIO_CMD_INIT,(DCL_CTRL_DATA_T *)&data_init);
print_bootup_trace_exit(SST_INIT_DRV1_UART2);
#ifdef __UART3_SUPPORT__
print_bootup_trace_enter(SST_INIT_DRV1_UART3);
// Register the callback function
uart_handle = DclSerialPort_Open(uart_port3, 0);
DclSerialPort_RegisterCallback(uart_handle,&Uart_Drv_Handler);
DclSerialPort_Control(uart_handle,SIO_CMD_INIT,(DCL_CTRL_DATA_T *)&data_init);
print_bootup_trace_exit(SST_INIT_DRV1_UART3);
#endif
}
