int ccci_util_fo_init(void)
{
int idx;
CCCI_UTIL_INF_MSG("ccci_util_fo_init 0.\n");
lk_meta_tag_info_collect();
// Parse META setting
ccci_parse_meta_md_setting(md_info_tag_val);
// Calculate memory layout
for(idx=0;idx<MAX_MD_NUM;idx++)
{
cal_md_settings(idx);
}
CCCI_UTIL_INF_MSG("ccci_util_fo_init 2.\n");
return 0;
}
void ccci_md_mem_reserve(void)
{
#ifndef CONFIG_ARM64
int reserved_size = 0;
phys_addr_t ptr = 0;
int i;
#if defined(CONFIG_OF)
lk_meta_tag_info_collect();
#if defined(FEATURE_DFO_EN) // DFO enable and using device tree
lk_dfo_tag_info_collect();
#endif
#endif
// Get MD memory requirements
collect_md_settings();
// For internal MD
for(i=0; i<4; i++) {// 0~3 for internal
if(modem_size_list[i] == 0)
continue;
reserved_size = ALIGN(modem_size_list[MD_SYS1+i], SZ_2M);
memblock_set_current_limit(0xFFFFFFFF);
ptr = arm_memblock_steal(reserved_size, CCCI_MEM_ALIGN);
memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
if(ptr) {
md_resv_mem_list[i] = ptr;
CCCI_UTIL_INF_MSG("md%d mem reserve successfully, ptr=0x%llx, size=0x%x\n", i+1, (unsigned long long)ptr, reserved_size);
}else{
CCCI_UTIL_INF_MSG("md%d mem reserve fail.\n", i+1);
}
}
// Parse META setting
ccci_parse_meta_md_setting(md_info_tag_val);
// Calculate memory layout
cal_md_mem_setting(MEM_LAY_OUT_VER);
#endif
}
