static int emu_lwl(struct pt_regs * regs,mips_instruction ir,vaddr_t_l emulpc)
{ int err = 0;
/*the "ir" is the instruction causing the exception*/
/*get the real address,perhaps the address is not word aligned*/
void *va = REG_TO_VA_l (regs->regs[MIPSInst_RS(ir)])+ MIPSInst_SIMM(ir);
unsigned long addr = 0;
unsigned long emul_pc = (unsigned long)emulpc;
unsigned long little_three_bits;
unsigned long value,value_tmp;
// printf("emu_lwl\r\n");
/*compute the correct position in the RT*/
/*note !!!!: we have supposed the CPU is little_Endianness and status regiester's RE bit =0 */
/*little Endianness*/
little_three_bits = (unsigned long)va&(0x7);
value_tmp = regs->regs[MIPSInst_RT(ir)];
switch(little_three_bits) {
case 0:
case 4:
/*must check lwl valid*/
addr = (unsigned long) va;
check_axs(emul_pc,addr,4);
value = mips_get_word_l(regs,va,&err);
if(err){
return SIGBUS;
}
value<<=24;
value_tmp &= 0xffffff;
regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
break;
case 1:
case 5:
addr = (unsigned long)va -1;
check_axs(emul_pc,addr,4);
value = mips_get_word_l(regs,(void *)((unsigned long) va-1),&err);
if(err){
return SIGBUS;
}
value<<=16;
value_tmp&=0xffff;
regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
break;
case 2:
case 6:
addr = (unsigned long)va - 2;
check_axs(emul_pc,addr,4);
value = mips_get_word_l(regs,(void *)((unsigned long)va-2),&err);
if(err){
return SIGBUS;
}
value<<=8;
value_tmp &= 0xff;
regs->regs[MIPSInst_RT(ir)] =value_tmp|value;
break;
case 3:
case 7:
addr = (unsigned long)va - 3;
check_axs(emul_pc,addr,4);
value = mips_get_word_l(regs,(void *)((unsigned long)va-3),&err);
if(err){
return SIGBUS;
};
regs->regs[MIPSInst_RT(ir)] = value;
break;
} /*swith ended*/
return 0;
}
static inline void
emulate_load_store_insn(struct pt_regs *regs,
unsigned long addr,
unsigned long pc)
{
union mips_instruction insn;
unsigned long value, fixup;
regs->regs[0] = 0;
/*
* This load never faults.
*/
__get_user(insn.word, (unsigned int *)pc);
switch (insn.i_format.opcode) {
/*
* These are instructions that a compiler doesn't generate. We
* can assume therefore that the code is MIPS-aware and
* really buggy. Emulating these instructions would break the
* semantics anyway.
*/
case ll_op:
case lld_op:
case sc_op:
case scd_op:
/*
* For these instructions the only way to create an address
* error is an attempted access to kernel/supervisor address
* space.
*/
case ldl_op:
case ldr_op:
case lwl_op:
case lwr_op:
case sdl_op:
case sdr_op:
case swl_op:
case swr_op:
case lb_op:
case lbu_op:
case sb_op:
goto sigbus;
/*
* The remaining opcodes are the ones that are really of interest.
*/
case lh_op:
check_axs(pc, addr, 2);
__asm__(
".set\tnoat\n"
#ifdef __BIG_ENDIAN
"1:\tlb\t%0,0(%1)\n"
"2:\tlbu\t$1,1(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tlb\t%0,1(%1)\n"
"2:\tlbu\t$1,0(%1)\n\t"
#endif
"sll\t%0,0x8\n\t"
"or\t%0,$1\n\t"
".set\tat\n\t"
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
:"=&r" (value)
:"r" (addr), "i" (&&fault)
:"$1");
regs->regs[insn.i_format.rt] = value;
return;
case lw_op:
check_axs(pc, addr, 4);
__asm__(
#ifdef __BIG_ENDIAN
"1:\tlwl\t%0,(%1)\n"
"2:\tlwr\t%0,3(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tlwl\t%0,3(%1)\n"
"2:\tlwr\t%0,(%1)\n\t"
#endif
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
:"=&r" (value)
:"r" (addr), "i" (&&fault));
regs->regs[insn.i_format.rt] = value;
return;
case lhu_op:
check_axs(pc, addr, 2);
__asm__(
".set\tnoat\n"
#ifdef __BIG_ENDIAN
"1:\tlbu\t%0,0(%1)\n"
"2:\tlbu\t$1,1(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tlbu\t%0,1(%1)\n"
"2:\tlbu\t$1,0(%1)\n\t"
#endif
"sll\t%0,0x8\n\t"
"or\t%0,$1\n\t"
".set\tat\n\t"
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
:"=&r" (value)
:"r" (addr), "i" (&&fault)
:"$1");
regs->regs[insn.i_format.rt] = value;
return;
case lwu_op:
check_axs(pc, addr, 4);
__asm__(
#ifdef __BIG_ENDIAN
"1:\tlwl\t%0,(%1)\n"
"2:\tlwr\t%0,3(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tlwl\t%0,3(%1)\n"
"2:\tlwr\t%0,(%1)\n\t"
#endif
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
:"=&r" (value)
:"r" (addr), "i" (&&fault));
value &= 0xffffffff;
regs->regs[insn.i_format.rt] = value;
return;
case ld_op:
check_axs(pc, addr, 8);
__asm__(
".set\tmips3\n"
#ifdef __BIG_ENDIAN
"1:\tldl\t%0,(%1)\n"
"2:\tldr\t%0,7(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tldl\t%0,7(%1)\n"
"2:\tldr\t%0,(%1)\n\t"
#endif
".set\tmips0\n\t"
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
:"=&r" (value)
:"r" (addr), "i" (&&fault));
regs->regs[insn.i_format.rt] = value;
return;
case sh_op:
check_axs(pc, addr, 2);
value = regs->regs[insn.i_format.rt];
__asm__(
#ifdef __BIG_ENDIAN
".set\tnoat\n"
"1:\tsb\t%0,1(%1)\n\t"
"srl\t$1,%0,0x8\n"
"2:\tsb\t$1,0(%1)\n\t"
".set\tat\n\t"
#endif
#ifdef __LITTLE_ENDIAN
".set\tnoat\n"
"1:\tsb\t%0,0(%1)\n\t"
"srl\t$1,%0,0x8\n"
"2:\tsb\t$1,1(%1)\n\t"
".set\tat\n\t"
#endif
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
: /* no outputs */
:"r" (value), "r" (addr), "i" (&&fault)
:"$1");
return;
case sw_op:
check_axs(pc, addr, 4);
value = regs->regs[insn.i_format.rt];
__asm__(
#ifdef __BIG_ENDIAN
"1:\tswl\t%0,(%1)\n"
"2:\tswr\t%0,3(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tswl\t%0,3(%1)\n"
"2:\tswr\t%0,(%1)\n\t"
#endif
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
: /* no outputs */
:"r" (value), "r" (addr), "i" (&&fault));
return;
case sd_op:
check_axs(pc, addr, 8);
value = regs->regs[insn.i_format.rt];
__asm__(
".set\tmips3\n"
#ifdef __BIG_ENDIAN
"1:\tsdl\t%0,(%1)\n"
"2:\tsdr\t%0,7(%1)\n\t"
#endif
#ifdef __LITTLE_ENDIAN
"1:\tsdl\t%0,7(%1)\n"
"2:\tsdr\t%0,(%1)\n\t"
#endif
".set\tmips0\n\t"
".section\t__ex_table,\"a\"\n\t"
STR(PTR)"\t1b,%2\n\t"
STR(PTR)"\t2b,%2\n\t"
".previous"
: /* no outputs */
:"r" (value), "r" (addr), "i" (&&fault));
return;
case lwc1_op:
case ldc1_op:
case swc1_op:
case sdc1_op:
/*
* I herewith declare: this does not happen. So send SIGBUS.
*/
goto sigbus;
case lwc2_op:
case ldc2_op:
case swc2_op:
case sdc2_op:
/*
* These are the coprocessor 2 load/stores. The current
* implementations don't use cp2 and cp2 should always be
* disabled in c0_status. So send SIGILL.
* (No longer true: The Sony Praystation uses cp2 for
* 3D matrix operations. Dunno if that thingy has a MMU ...)
*/
default:
/*
* Pheeee... We encountered an yet unknown instruction or
* cache coherence problem. Die sucker, die ...
*/
goto sigill;
}
return;
fault:
/* Did we have an exception handler installed? */
fixup = search_exception_table(regs->cp0_epc);
if (fixup) {
long new_epc;
new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
printk(KERN_DEBUG "%s: Forwarding exception at [<%lx>] (%lx)\n",
current->comm, regs->cp0_epc, new_epc);
regs->cp0_epc = new_epc;
return;
}
lock_kernel();
send_sig(SIGSEGV, current, 1);
unlock_kernel();
return;
sigbus:
lock_kernel();
send_sig(SIGBUS, current, 1);
unlock_kernel();
return;
sigill:
lock_kernel();
send_sig(SIGILL, current, 1);
unlock_kernel();
return;
}
